Silicon Light Machines Confidential

MCM Packaging Options

For

4096 I/O GLV Module

Prepared For

Michael Dueweke, Ph. D.

Silicon Light Machines

385 Moffett Park Dr.

Sunnyvale, CA 94089

By

Mike Patterson

(503) 318-7678

February 6, 2003

Silicon Light Machines Confidential Report

Contents

Definition of Design Goals and Challenges

Interconnect Options

Wire bond

Flip chip

Thru silicon vias

Comparison of Interconnect Options

Relative Electrical Assessment

List of Vendors and Contacts

Alternate Technologies

System Design Requirements and Assumptions

1) Die

GLV MEMS die: 22 x 22 mm, 4096 input pads split between two opposite sides. The resulting “effective interconnect pitch” is approximately 10µ.

Driver die:

  • Current design 6.2 x 16.64 x .686 mm.
  • 272 output pads on 60µ pitch corresponding to input pads on the GLV.
  • 60 input pads corresponding to global input pads to the MCM.
  • If current driver chips were used in this MCM, total # die = 4096/272 = 16
  • For purposes of this exercise, it is assumed that the size of the driver die to date is pad limited, and that changes in the i/o pad geometry can drive the relative size of the driver die. The ratio of input to output pads is ~4.5.

2) Optical Window

An optical window must be positioned such that the bottom of the glass is >5mm above the GLV surface. The thickness of the glass is 1.1 mm thick. The minimum size of the optical window is 18 mm square.

3) Thermal Dissipation

Power per driver chip ~1.75 W = 28 W total power.

4) Package

The total number of pins is estimated to be a maximum of 76 (60 inputs to the driver chip plus one unique signal per driver chip).

The package must be hermetic per Mil-STD-883 at 1 x 10-8.

Wire Bond Using Staggered Bond Pads

This approach would use three corresponding rows of offset bond pads on a 30µ pitch, for an effective pitch of 10µ. Current state of the art fine pitch ball bonding is 35µ pad pitch for in-line pads, using 15µ diameter wire in high volume production. Current state of the art “effective pitch” for triple row staggered pads is 20µ in a plastic molded package. The emphasis on the challenge is wire sweep during molding.

Extrapolating from existing published design rules, the resulting pad geometry would be ~24µ square bond pads at the first bond, and 24 x 60µ bond pads at the second bond. The smaller bond pads could be located on either the GLV or driver die.

View of 1st bond / View of 2nd bond

Wire bonding, stacked die

This technology is currently used in high volume applications, driven by flash memory and cell phone markets.

Standard practice is to use a silicon spacer or interposer between die to match the coefficient of thermal expansion and provide clearance for the wire bond loops.

The advantage of this approach is to relieve congestion on the driver die, and provide better thermal distribution for heat dissipation. A variation of this approach would put the ball bonds on the GLV and the second bond (called SSB bond by K&S) on the driver die. This would result in smaller bond pads on the GLV. Either way, 30µ pitch wire bonding is necessary when three die are stacked. More layers of stacked die can be used to increase the minimum pad pitch. Four stacked die would result a minimum 36µ pad pitch.

Flip chip to substrate

This option has both GLV and driver chips flip chip bonded to a substrate. Shown here is one possible array of bumps. The layout is two arrays of 32 x 64, with bumps on a 300µ grid. The minimum recommended pitch is 200µ, so this layout allows a conservative approach with higher yield and reliability. Assembly houses are routinely assembling large die with several thousand solder bumps.

One disadvantage is that the array faces the substrate, requiring an opening be cut in the interposer substrate. This complicates the design requirements of the final package. An example package design is shown below to illustrate these issues.

Flip chip on GLV

Another option for flip chip assembly is to bond the driver die directly to the GLV chip. The GLV then becomes the routing substrate for the driver die. This configuration simplifies the final package design greatly. The external pins could easily be wire bonded to a simple ceramic or metal package, shown here in a DIP configuration.

Thru Silicon Vias

This technology has been developed locally by Tru-Si Technologies. The process is to etch deep vias into the surface of the die, sputter a barrier metal, plug fill the vias with an appropriate metal, and the wafer is etched thin such that the bottom of the filled vias emerge as bumps on the back side of the wafer.

VIA SPUTTER FILL THIN

This can be accomplished on a 90µ array. The effect on simplifying the final package design is shown below. In this example, the package is shown in a BGA configuration.

Tru-Si has developed a partnership with OSE USA in San Jose to develop and qualify this process. It has yet to go to production.

Relative Comparison of Interconnect Options

Wire Bond, Staggered / Wire Bond, Stacked / Flip Chip on Substrate / Flip Chip on GLV / Thru Si Vias on Substrate
Risk / High / High / Low / Low / Medium
Assembly Yield / Low / Low / High / High / Medium
Thermal / Low / Medium / High / High / High
Package Size / Large / Medium / Medium / Small / Medium
Speed to implement / Fast / Medium / Slow / Medium / Slow
Cost / Lowest / Low / Highest / Medium / Medium
Mechanical stability / High / High / Medium / High / High
Scalability / Low / Low / Medium / High / High

Relative Comparison of Electrical Performance

Wire Bond / Flip Chip
Trace Inductance / 4 – 5 nH / 2 – 3 nH
Trace Capacitance / .9 – 1.3 pF / 1.2 – 1.9 pF
Trace Resistance / 110 – 150 mOhm / 220 – 350 mOhm
PWR trace inductance / .1 - .15 nH / .02 - .2 nH
GND trace inductance / .02 - .03 nH / .003 - .008 nH
PWR trace resistance / 2.8 – 3.8 mOhm / .17 – 2.7 mOhm
GND trace resistance / .5 - .7 mOhm / .03 - .05 mOhm
Ground Bounce Noise at 100 MHz / 3 x 10-3 V / 8 x 10-4 V
At 500 MHz / 1.5 x 10-2 V / 4 x 10-3 V
At 1 GHz / 2.9 x 10-2 V / 8 x 10-3 V

Note: These numbers are for an organic substrate, and should be used for relative comparison only.

List of Vendors and Contacts:

  1. Assembly Houses
  • ChipPak
  • Fine pitch wire bonding and flip chip assembly. Known 20µ effective pitch capability.
  • Scott Lindseth, Sr. Dir of Sales, 510-979-8298
  • OSE
  • Fine pitch wire bonding, flip chip assembly, and thru-silicon via assembly development.
  • Medium volume production and process development located in San Jose, with over seas facilities for higher volumes.
  • Chris Ooi, VP Sales & Operations, 408-321-3600
  1. ASE
  2. High volume, high i/o flip chip assembly
  3. Jennifer Yuen, Sales Director, 408-986-6500
  1. Technology Development
  1. Tru-Si
  2. Wafer thinning and thru-silicon via processing.
  3. Pat Halahan, CTO, 408-720-3341
  4. Enabling Technologies
  5. High speed design and analysis services
  6. Manoj Nachnani, President, 408-573-1325
  7. Ixion Ceramics
  8. Full product line of custom ceramic and metal package design and fabrication capability, including optical window lids.
  9. Brian Bukovitz, Account manager, 423-755-5510
  10. MTB Solutions
  11. Advanced packaging technology consultants. Flip chip design solutions up to 40 GHz. Technology partners with ASE for assembly.
  12. Mark Diorio, VP Sales, 408-570-9710
  13. Pixel Interconnect
  14. Advanced packaging technology consulting. Experienced in optical networking solutions.
  15. Scott Cockey, CEO, 503-885-8444

Other Technologies of interest

  • Ziptronix has developed a process to hermetically seal optical MEMS devices at the wafer level. This process allows standard assembly processes to be used.
  • Accu-Mold claims to be able to manufacture hermetically sealed plastic packages that conform to MIL STD 883 E Method 1014, Condition A4, at 1 x 10-8.

Mike PattersonFebruary 7, 2003Page 1 of 11