University of LeicesterPLUMERef: PLM-SYS-MasterSoftware-606-0
Date: 19/08/2009
Master software interface document
Philip Peterson
Date / Updated Reference Number / change19/08/2009 / PLM-SYS-MasterSoftware-606-0 / Preliminary version
03/11/2009 / PLM-SYS-MasterSoftware-606-1 / Modified OBDH-PAY pins according to change in master electronics interface document
[dd/mm/yyyy] / [PLM-XXX-XXX-xxx-x] / [eg. first draft]
Introduction
This master document defines the format of communications between the various subsystems – who is talking to who, and how. It does not contain information on power supplies and grounding, or pin designations.Where any disparities have arisen between this document and individual subsystem documentation, it is the responsibility of the team in question to point out the mistake to the systems engineer or to edit their documentation to comply with the master document.
Should pin designations need to be changed, changes must first be compared to the master electronics interface document, which has precedence. If there are any inconsistencies between this document and the master electronics interface, assume that the electronics document is correct.
Definitions
The format field expresses what kind of voltage range can be found particular pin, along with a maximum current rating in brackets. The formats used in satellite communications are as follows:
- 5V Logic: Logic pin with 5V representing binary 1 and 0V representing binary 0.
- 3.3V Logic: Logic pin with 3.3V representing binary 1 and 0V representing binary 0. These pins can withstand between -0.3V and 3.6V. The power draw from the OBDH board should not exceed 48mA for all the 3.3V TTL pins combined.
- I2C: Voltages on this pin are compatible with the I2C protocol.
- ±2.5V analog: Analog signal pin that swings between -2.5V to +2.5V. This voltage range is the only one compatible with the MCU’s ADC.
Each subsystem uses either analog or digital electronics. This is important to software communications because analog logic and commands are not usually time sensitive. Digital commands, on the other hand, are precisely timed and ordered sequences of bits with the timing provided by one or more clock signals. Digital interfaces can control a great variety of functions using only a few I/O pins, but analog interfaces require one pin for each function.
OBDH-ADCS Communication
The OBDH and ADCS use four pins for communication:
Pin ID / Pin name and description / Direction / FormatH1.1 / I/O Port 5.7: ADCS_RESET: Set./reset function for ADCS. / OBDH>ADCS / 3.3V Logic
H1.3 / I/O Port 5.5: MAX_10: ADCS axis select MSB / OBDH>ADCS / 3.3V Logic
H1.5 / I/O Port 5.3: MAX_9: ADCS axis select LSB / OBDH>ADCS / 3.3V Logic
H2.3 / I/O Port 6.5:READ_ADCS: Magnetic strength, use with H2.20, H2.22 / ADCS>OBDH / ±2.5V Analog
Table 1: ADCS communication pin designation
The ADCS system contains a three axis magnetometer, with one analog output per axis. These outputs are interfaced to the OBDH system through a four-channel multiplexer. The selected axis is determined using the MAX_9 and MAX_10 pins. The truth table for these pins is shown on table 2:
MAX_10 / MAX_9X axis / Low / High
Y axis / Low / Low
Z axis / High / Low
No Connection / High / Low
Table 2: ADCS truth table
The ADCS uses analog circuitry and logic, and has a well definedstartup and operating procedure for the OBDH system to follow given in its software interface document.
The analog output of the ADCS system should vary between -2.5V and +2.5V referenced to analog ground. 0V corresponds to a magnetic field fully perpendicular to the axis selected with MAX_9 and MAX_10. The precise field strength to voltage ratio should be linear, but the ADCS system has not yet been calibrated.
The ADCS_RESET pin controls the magnetometer’s set/reset function. Every time this pin transitions, the set/reset circuitry on the ADCS board produces a brief, fairly strong magnetic field across the magnetometer. After use, the magnetometer must be left to ‘settle’ for a few seconds. To set/reset the magnetometer, transition the ADCS_RESET pin, wait two microseconds, and transition it again. The initial state of the pin does not matter; either high-low-high or low-high-low will do. More details on the set/reset procedure are given in the ADCS software interface document.
OBDH-PSU Communication
The OBDH and PSU communicate on five pins (table 3).
Pin ID / Pin name and description / Direction / FormatH1.21 / I/O Port 3.3: Alternate I2C clock / OBDH>PSU / I2C
H1.23 / I/O Port 3.1: Alternate I2C data / OBDH>PSU / I2C
H1.24 / I/O Port 3.0: ON_I2C: Controls offboard isolator for I2C / OBDH>PSU / 3.3V Logic
H1.41 / SDA_SYS: I2C Data / OBDH>PSU / I2C
H1.43 / SCL_SYS: I2C Clock / OBDH>PSU / I2C
Table 3: PSU communication pin designation
The PSU has an onboard microprocessor and uses digital signals to communicate.
When the ON_I2C pin is high, the I2C bus is active and messages may be sent. The PSU subsystem is the only one to communicate using I2C, with the OBDH system acting as master and the PSU as slave.
Until a copy of the Clydespace power supply manual can be located, further information on the software interface between PSU and OBDH is unavailable.
OBDH-COMS Communication
Seven pins make up the OBDH-COMS interface (table 4).
Pin ID / Pin name and description / Direction / FormatH1.33 / +5V_SW: Power for COMS transceiver, controlled by OBDH. / OBDH>COMS / 5V Power (see H2.25)
H1.34 / -RST_MHX: Transceiver reset, active when low / OBDH>COMS / 5V Logic
H1.35 / -CST_MHX: Transceiver clear to send, active when low / COMS>OBDH / 5V Logic
H1.36 / -RTS_MHX: Transceiver request to send, active when low / OBDH>COMS / 5V Logic
H1.37 / -DSR_MHX: Transceiver data set ready, active when low / COMS>OBDH / 5V Logic
H1.38 / -DTR_MHX: Transceiver data terminal ready, active when low / OBDH>COMS / 5V Logic
H1.39 / TXD_MHX: Transceiver transmit data, idles high / OBDH>COMS / 5V Logic
H1.40 / RXD_MHX: Transceiver receive data, idles high / COMS>OBDH / 5V Logic
Table 4: COMS communication pin designation
The COMS system uses digital signals to communicate, and has its own specially designated communication pins.
COMS has two main components: the transceiver itself, and a PIC modem through which the transceiver communicates with OBDH.
The +5V_SW pin is included in this software document because it is controlled by the MCU software. Before any transmissions can be sent or received, power must first be routed to the transceiver through the MCU.
The modem itself is half-duplex; it cannot transmit and receive at the same time. Information on communicating with the modem is available in the RF-DataTech manual [1] section 6.1.
OBDH-PAY Communication
The payload communicates with OBDH throughseventeen pins (table 5)
Pin ID / Pin name and description / Direction / FormatH2.1 / SIGNAL_X: Payload X detector signal output / PAY>OBDH / ±2.5V Analog
H2.8 / SIGNAL_Y: Payload Y detector signal output / PAY>OBDH / ±2.5V Analog
H2.4 / HV_IN_X: X detector HV input sense / PAY>OBDH / ±2.5V Analog
H2.5 / HV_IN_Y: Y detector HV input sense / PAY>OBDH / ±2.5V Analog
H2.6 / HV_OUT_X: X detector HV output sense / PAY>OBDH / ±2.5V Analog
H2.7 / HV_OUT_Y: Y detector HV output sense / PAY>OBDH / ±2.5V Analog
H2.12 / RESET_X: Payload X detector sample hold reset / OBDH>PAY / 3.3V Logic, active high
H2.13 / RECIEVED_X: Payload X detector signal received / PAY>OBDH / 3.3V Logic, active high
H2.14 / RESET_Y: Payload Y detector sample hold reset / OBDH>PAY / 3.3V Logic, active high
H2.15 / RECIEVED_Y: Payload Y detector signal received / PAY>OBDH / 3.3V Logic, active high
H1.8 / I/O Port 5.0: HV_SET_x1: High voltage transformer control DAC bit 0 / OBDH>PAY / 3.3V Logic
H1.7 / I/O Port 5.1: HV_SET_x2: High voltage transformer control DAC bit 1 / OBDH>PAY / 3.3V Logic
H1.6 / I/O Port 5.2: HV_SET_x4: High voltage transformer control DAC bit 2 / OBDH>PAY / 3.3V Logic
H1.13 / I/O Port 4.3: SUPPORT_ON_X: Hold high to enable X detector support. / OBDH>PAY / 3.3V Logic
H1.14 / I/O Port 4.2: SUPPORT_ON_Y: Hold high to enable Y detector support / OBDH>PAY / 3.3V Logic
H1.15 / I/O Port 4.1: HV_ON_X: Hold high to turn on X HV transformer / OBDH>PAY / 3.3V Logic
H1.16 / I/O Port 4.0: HV_ON_Y: Hold high to turn on Y HV transformer / OBDH>PAY / 3.3V Logic
Table 5: PAY communication pin designation
The payload uses analog electronics, and consists of two redundant detectors – X and Y. For all functions except setting the HV output level, two pins are allocated, one for each detector.
Four logic pins are used to turn on and off different parts of the subsystem. The SUPPORT_ON pins activate the signal processing and safety mechanisms for either the X or Y detector when high. These subsystems must be active for any of the analog voltage outputs to be meaningful, and as a precaution the HV_ON pins have no effect on a detector until the detector’s SUPPORT_ON pin is high.
The HV_ON pins are held high to power up the high voltage transformer for a detector. Only when the both power pins are high can a detector be used to take measurements. Full startup, shutdown and error procedures for the payload are available in the payload’s software interface document.
The HV_SET pins control a three-bit digital analog converter that is used to control the voltage of the HV transformer. Unlike most of the other payload pins, HV_SET controls both detectors.
The payload includes voltage monitoring circuitry, which provides advance warning that a detector may be about to die. HV_IN is proportional to the input voltage of the HV transformer, and HV_OUT is proportional to the HV output. Conversion factors are given in the software interface document.
Three pins of each detector are used to make measurements. The SIGNAL pin carries the signal output from the detector. Each detector is expected to receive about ten events per day, and when an event occurs the RECEIVED pin for the respective detector will go high. This will produce an interrupt in the MCU. A sample-hold circuit is used to hold the voltage on the SIGNAL pin until the MCU can retrieve it. To reset the sample hold circuit after the measurement has been taken, hold the RESET pin high for at least one microsecond and then low again. The RESET pin should be held low at all other times.
OBDH-CAM Communication
The camera uses sixteen pins to communicate with OBDH (table 6)
Pin ID / Pin name and description / Direction / FormatH1.17 / I/O Port 3.7: Camera clock (SIO_C) / OBDH>CAM / 3.3V Logic
H1.18 / I/O Port 3.6: Camera data (SIO_D) / OBDH>CAM / 3.3V Logic
H1.19 / I/O Port 3.5: Camera VSYNC, goes high when new frame starts / CAM>OBDH / 3.3V Logic
H1.20 / I/O Port 3.4: Camera HREF, goes high for new pixel row / CAM>OBDH / 3.3V Logic
H1.22 / I/O Port 3.2: Camera PCLK, goes high for each pixel byte / CAM>OBDH / 3.3V Logic
H2.16 / I/O Port 1.0: CAM_EN: Hold high to enable the camera / OBDH>CAM / 3.3V Logic
H2.17 / I/O Port 2.7: Camera data Y7 / CAM>OBDH / 3.3V Logic
H2.18 / I/O Port 2.6: Camera data Y6 / CAM>OBDH / 3.3V Logic
H2.19 / I/O Port 2.5: Camera data Y5 / CAM>OBDH / 3.3V Logic
H2.20 / I/O Port 2.4: Camera data Y4 / CAM>OBDH / 3.3V Logic
H2.21 / I/O Port 2.3: Camera data Y3 / CAM>OBDH / 3.3V Logic
H2.22 / I/O Port 2.2: Camera data Y2 / CAM>OBDH / 3.3V Logic
H2.23 / I/O Port 2.1: Camera data Y1 / CAM>OBDH / 3.3V Logic
H2.24 / I/O Port 2.0: Camera data Y0 / CAM>OBDH / 3.3V Logic
Table 6: CAM communication pin designation
The camera board incorporates its own microprocessor and as such uses predominantly digital communications. Communication takes place using a serial-like interface, with SIO_C acting as clock and SIO_D carrying data. The interface uses a proprietary standard, the SCCB (serial camera control bus). Changing camera variables can alter such things as frame rate, brightness and colour format. See reference [2] for more information on SCCB, as well as a command list.
The CAM_EN pin controls power to the camera. To turn the camera on, hold the pin high; otherwise hold it low.
The camera is a video camera; all the time it is active it will be transmitting pixel data via the Y0..7 pins. The camera has an image array size of 640x480, and by default it scans this array row by row, with each pixel’s color data being transmitted on Y0..7. Timing information is provided by the VSYNC, HREF and PCLK pins. PCLK constantly oscillates, transitioning high when a new byte of pixel information is ready. HREF is normally high, but transitions low on the last pixel of every horizontal row. VSYNC is normally low, but transitions high between frames. Timing diagrams for these pins are available in reference [3]
References
[1] (retrieved 21st August 2009) – RF DataTech
[2] (retrieved 21st August 2009) – Omnivision technologies inc.
[3] (retrieved 21st August 2009) – Omnivision technologies inc.
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