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Low Power Testing
Zdeněk Kotásek, Jaroslav Škarvada
BrnoUniversity of Technology, Faculty of Information Technology, Božetěchova 2, 612 66 Brno, CzechRepublic
Abstract
Portable computer systems and embedded systems are examples of electronic devices which are powered from batteries; therefore, they are designed with the goal of low power consumption. Low power consumption becomes important not only during normal operational mode, but during test application as well when switching activity is higher than in normal mode. In this chapter, a survey of basic concepts and methodologies from the area of low power testing is provided. It is explained here how power consumption is related to switching activities during test application. The concepts of static and dynamic power consumption are discussed together with metrics which can be possibly used to evaluate power consumption. The survey of methods, the goal of which is to reduce dynamic power consumption during test application, is then provided followed by a short survey of power-constrained test scheduling methods.
INTRODUCTION
Power consumption of an electronic component is different for various technologies and platforms. CMOS technology is a dominant technology used in VLSI design (Nicolici & Al-Hashimi, 2003). A CMOS gate structure can be seen in Figure1.
Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn while the transistors in a CMOS device are switching between on and off states. CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic which uses all n-channel devices without p-channel devices. CMOS also allows a high density of logic functions on a chip. It was primarily this reason why CMOS won the race in the eighties and became the most used technology to be implemented in VLSI chips. Consequently, to develop methodologies which allow us to reduce power consumption during test application became a necessity.
The diagram of power consumption during test application is shown in Figure 2. Test vectors V1 – V7 are applied at t1 – t7, ti = i/f; i = (1;7) is a pulse sequential index, f is the frequency of clock pulses. In the figure, the test per clock (TPC) strategy is demonstrated here in which one test vector is applied by one clock pulse and a response is gained. If the test is applied through a scan register then the test per scan (TPS) strategy is used.During one test step several clock pulses are applied.
Figure1. CMOS gate
Figure 2. Diagram of power consumption during test application
Power consumption value can be evaluated by means of the following formula (Raghunathan, Jha & Dey, 1998;Roy & Prasad, 2000):
p(t) = ps(t) +pd(t) (1)
where p(t) represents power consumption at time t, ps(t)which is the static power consumption, while pd(t) is the dynamic power consumption.
It is evident that switching activity plays an important role in considerations about power consumption of electronic component. The objective of this chapter is to primarily explain the relation between the range of switching activity in VLSI components and power consumption. It is a well known fact that power consumption is higher during test application than during normal operation, therefore special attention is paid to techniques which have as its goal to reduce power consumption during test application (Girard, Nicolici Wen, 2010).
Static Power Consumption Ps
The value of ps(t) is not changing in time, therefore it can be marked as Ps. It can be enumerated by means of the following formula:
(2)
In (2), the symbols have the following meaning: Idiode– reversal current between diffusion area and substrate, Isubtreshold – leakage current (see formula3), Udd – supply voltage
(3)
In (3), the constants depend on the technology level of transistors used in the design. The meaning of the symbols is as follows: Weff - effective width of transistor channel, Uin - the value of input voltage, UT - the value of threshold voltage. The value of Psincreases exponentially with a decreasing UT value. In most technologies used in 2008 - 2009, the value of Ps is not more than 50% of total power consumption value. In a significant number of electronic components produced in older technologies, it is even less--not more than 10%. The Ps value is constant in time and does not depend on input signals (see Ps in Figure2).
Dynamic Power Consumption pd(t)
The value of pd(t) depends on the status of an electronic component in time t. In CMOS technology, it reaches the highest values when a transistor switches its state (0→ 1, 1→ 0). To calculate the mean value of dynamic power consumption Pd in <( i – 1)/f ; i/f) [s] interval, then the value of Pd for electronic component consisting of CMOS gates can be calculated as the sum of PSW and PSC (formula 4) (Raghunathan, Jha & Dey, 1998;Roy & Prasad, 2000). The waveform demonstrating power consumption is then represented by a discrete diagram (Figure 3), in contrast to Figure2 where power consumption is represented by a continuous diagram.
Figure3. Discrete power consumption diagram
(4)
The PSW expression is denoted as the consumption caused by switching parasite capacities (charging and discharging) – see formula 5. The PSC expression consists of power consumption caused by a short circuit Udd → GROUND during transitions 1→ 0, 0 → 1 when both transistors NMOS and PMOS are open (see Figure2)
(5)
The symbols have the following meaning: CL – capacity of gates, Udd - supply voltage, n(i) – the number of transitions 1→ 0, 0 → 1, when the component changes its state in (i – 1)/f time to the opposite state in i/f time.
To evaluate PSC the following formula can be used:
(6)
The symbols have the following meaning: K – the constant depending on the type of transistors, UT – the value of threshold voltage, τ – duration time of signals rising / falling edges, Udd - supply voltage, n(i) – the number of transitions 1→ 0, 0 → 1, when the component changes its state in (i – 1)/f time to the opposite state in i/f time, f – clock signal frequency.
When all the formulas are substituted into 1, then the result is reflected bythe following formula:
(7)
This model can be further extended for the evaluation of power consumption mean value in (i1/f ; i2/f), [s] interval, i1 < i2:
(8)
For energy dissipated during <i1/f ; i2/f > [s] interval, i1 < i2, a generally applicable formula can be used:
(9)
Mean power dissipated during i1/f ; i2/f [s] interval, i1 i2, can be evaluated by means of the following formula:
(10)
It is important to say that the impact of internal delays must be considered as well because it can be a hazard and cause additional power consumption as a consequence. The delay of a gate can be calculated by means of the following formula:
(11)
In the formula, α represents saturation delay [for CMOS 0,18 μ usually 1,3, Ln, Wn, Lp are geometric parameters of transistors (lengths and widths) of MOS transistors, Kn, Kp are transistor constants]. The remaining symbols were used in the previous formulas.
Power Consumption Metrics
Various formulas to evaluate power consumption were developed and implemented (Raghunathan, Jha & Dey, 1998;Roy & Prasad, 2000). They are difficult to use in practical designs, especially for complex circuits and a great volume of input data (test vectors). For the purposes of comparing various optimizing procedures aiming at power consumption reduction, power consumption metrics were developed and are used. It is evident that if the sequence of input data is reorganized as a result of applying a particular methodology and the implementation of the component is unchanged, then for the purposes of comparing various methodologies, anNTC (Number of Transition Count) parameter can be used. More precise techniques are based on the use of WNTC (Weighted Number of Transition Count) (Nicolici & Al-Hashimi, 2003) and WSA (Weighted Switching Activity) (Debjyoti, Swarup & Kaushik, 2003). These parameters can be evaluated by the following formulas:
(12)
In the formula, n(i) represents the number of transitions 0→ 1, 1 → 0 between two states in i – 1/f , i /f instants, Nc is the total number of clock pulses applied during test application.
(13)
In the formula, the meaning of nj(i) and Nc is the same as in previous formula, Fj is the fan out factor of node j, NG is the total number of nodes in the component.
(14)
In the formula, Cj is a normalized node capacity and the meaning of other symbols is the same as in previous formulas.
With the continuing increase in chip density, power dissipation has become a major design constraint for today’s VLSI circuits. Although there are many techniques for power minimization during normal (functional) operation, power minimization during testing is an emerging research area because power dissipation during testing is becoming a yield and reliability problem. There is significantly more switching activity during testing than during functional operation. The increased switching activity can decrease the reliability of the circuit during testing because it causes excessive temperature and current density in which circuits designed with power minimization techniques cannot tolerate. Furthermore, as a result of high activity in circuits employing BIST, the voltage drop that only occurs during testing causes some good circuits to fail the testing process leading to unnecessary manufacturing yield loss.
To summarize, excessive switching activity during scan testing can cause average power dissipation and peak power during a test to be much higher than during normal operation. This can cause problems both with heat dissipation and current spikes.
Power consumption DuRing Test appliCAtion
Power Consumption Metrics for Test Application through Scan Registers
If TPS (Test Per Scan) strategy is used to apply a test, then the number of steps will increase m times, m is the number of registers in a scan chain. Thus, for complex components time needed to calculate power consumption values with the use of the above described formulas can be extended significantly. Therefore for power consumption during test application through scan registers, simplified formulas were developed. These formulas do not take into account transitions between states of the logic connected to scan registers during scan-in/scan-out phases; the preciseness of these evaluations is therefore decreased. These formulas can be used for scan registers which are isolated from logic circuitry during scan operations. NTC for the test vector scan-in phase applied through a scan chain can be calculated with the use of formula (15); and for the test response scan-out phase formula (16) can be used. The total NTC covering both phases can be calculated by means of formula (17)(Sankaralingham, Oruganti & Touba, 2000).
(15)
(16)
In the formulas in (15) and (16),Vi is a test vector consisting of m bits which will be loaded to a scan chain consisting of m registers, Vo is the response to Vitest vector.
(17)
These formulas can also be used for simplified calculations of WNTCand WSA metrics for scan chain - formulas(18) and (19).
(18)
In formula (18), Favg parameter reflects the average fan-out of scan chain register outputs.
(19)
Similarly, Cavg parameter represents the average normalized capacitance load of scan chain registers outputs.
Approximation models
In order to represent power consumption, a vector of real figures is needed with the length equal to the number of clock pulses (in the case of TPC strategy the number of test vectors too – see Figure3). In some situations, like test scheduling, it is not effective to work with this great amount of data but to approximate power consumption for all distinguishable sections of the test. The following requirements must be satisfied by the approximation model:
Simplicity – the approximation model must be simple enough to achieve low computational complexity.
Safety – the approximation model must be safe enough; the results gained by the approximation model must not decrease thermal effects compared with the real component.
Precision – the approximation model must be precise enough; it should reflect thermal effects of power consumption precisely without any overestimation of these effects.
Very often power consumption is approximated to Ptest scalar value which can then be used in such operations like comparing and adding. Ptestvalue can be determined as the maximum value of power consumption during test application (Figure4). Power consumption calculated in this way can be seen as a safe power consumption value because during test application it will certainly not become higher, but for practical use it is overvalued. The goal of test scheduling methods considering power consumption (to reduce Pmax) is to reduce the effects of overheating a component in which the test is applied. The peak values of power consumption are not destructive for electronic components because in their behavior thermal inertia exists. When approximating Ptest to a maximal value then time needed to apply the test can become longer. Another possibility is to approximate Ptestto the mean value of power consumption. In this case, it must be verified whether the model is safe enough due to thermal inertia of the component for which the test schedule is developed.
Figure 4. Ptest approximation related to maximal power consumption
a Survey of Existing Approaches to reduce Power consumption During Test Application
Two approaches for low power testing exist: the first ones are directed to reducing dynamic power consumption (switching power), while the other methodologies have the goal of reducing static power consumption (leakage power). It is important to state that in older implementations, dynamic power consumption was higher than the static one. In (Veendrick, 1984), it is reported that the dynamic power consumption is about 90% of the total power consumption. Thus, there was no need to pay much attention to methodologies aiming at the reduction of static power consumption.
It is evident that a very effective way on how to reduce dynamic power consumption is through the reduction of supply voltage (the function expressing the relation between power consumption and supply voltage is a quadratic function). Therefore, it is a trend in modern VLSI technologies to have the power supply voltage lower than in previous technologies. To maintain the value of noise immunitywith the reduction of supply voltage, threshold voltage must be reduced as well which causes the static power consumption to rise exponentially. As a consequence, in 90 nm technology the dynamic power consumption is 58% of total power consumption. According to (Thompson,Packan & Bohr, 1998), 65 nm technology is seen as the technology in which the values of static power consumption begins to prevail over the dynamic one. It is even more evident in technologies with higher levels of integration (32 nm, 25 nm) in which the static power consumption is higher than the dynamic one (Thompson,Packan & Bohr, 1998). Thus, to choose proper and effective optimizing procedures to decrease power consumption, the information about the target technology in which the design will be implemented becomes important.
Another criterion to be used to categorize methods reducing power consumption is based on categorizing test set developed to test the component under design. In this way, Test Set Dependent (TSD) and Test Set Independent (TSI) methods can be distinguished (Nicolici & Al-Hashimi, 2003). TSD based methods use both test and circuit structure modifications, while TSI based methods are based on circuit structure modification and the power reduction consumption is independent of the test set used. This categorization is usually used for the dynamic power consumption and the methods for static power reduction can be categorized as TSI methods.
The methods for power reduction during test application are used for reasons which are obvious from the following mechanism.
Let:
- P1 be mean power consumption value during test application before applying power optimizing procedure
- P2 be the mean power consumption during test application after applying power optimizing procedure
- t1 be test application time before applying power optimizing procedure
- t2 be test application time after applying power optimizing procedure.
Then, the methods satisfying the condition P1t1 > P2t2 allow us to reduce power consumption during test application. As a result, the operation time of batteries supplying power to a device beingtested is extended and energy is saved.
In the literature, these methods are not explicitly distinguished by their principle. Many optimizing methods are based on the iteration principle in which in every step the quality of partial solution is verified. Therefore, a precise comparison of optimizing procedures must be involved in these approaches. It is also important to develop methods which allow us to evaluate power consumption during test application.
Power Consumption Evaluation
It is evident that direct measuring of voltage and current delivered to a device being tested is certainly the most precise and reliable evaluation of power consumption during the test application. This approach is very difficult to be applied, especially in implementations operating on high frequencies near the limits of technologies. Analog measuring devices are not convenient for these purposes due to subsequent difficult processing. Digital devices must be able to sample the measured values with higher frequency compared to the operating frequency of devices being measured, minimally twice as high as the operating frequency according to the Nyquist-Shannon theorem (Shannon, 1949). Measuring devices satisfying these requirements are very expensive. Sometimes it is required to identify power consumption of internal components where in these situations the direct measurement is impossible. To avoid this, indirect methods can be used which are based on measuring temperature during the test application (Altet & Rubio, 2002).From this value, power consumption can be calculated. Due to thermal inertia, not very precise results are gained which does not allow us to compare optimizing procedures. To gain higher precision, more sensors can be used. If optimizing methods are used the goal of which is to modify the circuit structure then a great number of prototypes should be produced and measured which is impossible because of the necessary expense needed to apply such methods. Therefore, various statistical and simulation methods are used to evaluate the results of optimizing procedures. These procedures usually use some simplifying metrics. To compare the quality of solutions aiming at reducing power consumption, NTC appears to be an applicable metric. For a better comparison of solutions, other metrics can be used (WNTC, WSA, . . .). In order to gain the highest possible precision during simulation, it is necessary to work with the immediate value of power consumption which is computationally a complex problem.
Statistical methods for power consumption specification indicate low computational complexity (high speed) but also lower precision (Ravi, Raghunathan & Chakradhar, 2003). These methods work with such data as the type and the number of elements in the component, average fan-out in the component, the length of scan register, etc. In (Ravi, Raghunathan & Chakradhar, 2003), the following simulation methods are distinguished: methods utilizing full synthesis (simulation on physical level), methods utilizing limited synthesis and the so-called black boxes method. In the first group of simulation methods, the simulation is performed on the level of chip physical layout. The simulation is not only the most precise one, but the most time consuming one too. In the second group of methods, the design is mapped to the predefined set of elements (technological library). From models in the library, simulation data with required accuracy needed for simulation can be gained. These models are developed by means of simulation on a physical level and the results are possibly verified via measurement. The black boxes method is based on grouping selected components into blocks (black boxes). On these blocks, the responses on predefined input data are gained. During simulation the responses to input data are gained through extrapolation/interpolation from responses gained in the previous step.