Lesson-9 OPERATORS

Lesson-9 OPERATORS

VHDL has a wide set of different operators, which are used to perform some operation on the data types. Not all operators can operate on all data types. The operators in VHDL are further divided into groups of the same precedence level (priority). These operators with higher priority are listed in upper rows and with lower priority in lower rows, so upper row operators have highest priority and ones in bottom row have the least priority. The table below lists operators grouped according to priority level, highest priority first.

Class / Operator Precedence

Low
high / Same Operator Precedence (Applied Left –to-Right)
1. Logical operators / and / or / nand / nor / xor / xnor
2. Relational operators / = / /= / <= / >=
3. Shift operators / sll / srl / sla / sra / rol / ror
4.Addition operators / + / =
5. Unary operators / + / -
6. Multiplying op. / * / / / mod / rem
7. Miscellaneous op. / ** / abs / not

The order of precedence is the highest for the operators of class 7, followed by class 6 with the lowest precedence for class 1. Unless parentheses are used, the operators with the highest precedence are applied first. Operators of the same class have the same precedence and are applied from left to right in an expression. As an example, consider the following std_ulogic_vectors, X (=’010’), Y(=’10’), and Z (‘10101’). The expression

notX & YxorZrol1

is equivalent to((notX) & Y)xor(Zrol1)= ((101) & 10)xor(01011)=(10110)xor(01011) = 11101. The xor is executed on a bit-per-bit basis.

The description of the above operators are given below with the help of examples.

miscellaneous operators / ** , abs, not / The STD_LOGIC_VECTOR data type can be used in addition and subtraction operations (+ and -) if the STD_LOGIC_SIGNED or the STD_LOGIC_UNSIGNED package of the IEEE library is used.
(Otherwise the arithmetic operators can only be used with INTEGER, SIGNED and UNSIGNED data types)
multiplying operators / *, / , mod, rem

The remainder (rem) and modulus (mod) are defined as follows:

AremB = A –(A/B)*B(in which A/B in an integer)

AmodB = A – B * N(in which N is an integer)

The result of theremoperator has the sign of its first operand while the result of themodoperators has the sign of the second operand.

Some examples of these operators are given below.

11rem4results in 3

(-11)rem4results in -3

9mod4results in 1

7mod(-4)results in –1(7 – 4*2 = -1).

sign operators / + , -
adding operators / + , - , &

signalMYBUS:std_logic_vector (15downto0);

signalSTATUS:std_logic_vector (2downto0);

signalRW, CS1, CS2:std_logic;

signalMDATA:std_logic_vector ( 0to9);

MYBUS <= STATUS & RW & CS1 & SC2 & MDATA;

Other examples are

MYARRAY (15downto0) <= “1111_1111” & MDATA (2to9);

NEWWORD <= “VHDL” & “93”;

shift operators / Sll, srl, sla, sra, rol, ror / can only be used on BIT_VECTOR data types

variableNUM1:bit_vector := “10010110”;

NUM1srl2; -- will result in the number “00100101”.

When a negative integer is given, the opposite action occurs, i.e. a shift to the left will be a shift to the right. As an example

NUM1srl–2 would be equivalent to NUM1sll2 and give the result “01011000”.

Other examples of shift operations are for the bit_vector A = “101001”

variableA: bit_vector :=”101001”;

Asll2 --resultsin “100100”

Asrl2 --results in“001010”

Asla2 --results in“100111”

Asra2 --results in“111010”

Arol2 --results in“100110”

Aror2 --results in“011010”

relational operators / = (equal)
/= (not Equal)
< (less than)
<= (Less than equal to)
> (Less than)
>=(Greater than equal to) / BIT and BIT_VECTOR
STD_LOGIC and STD_LOGIC_VECTOR
(also on STD_ULOGIC,
STD_ULOGIC_VECTOR,
INTEGER,
SIGNED and UNSIGNED)

variableSTS: Boolean;

constantA: integer :=24;

constantB_COUNT: integer :=32;

constantC: integer :=14;

STS <= (A < B_COUNT) ; -- will assign the value “TRUE” to STS

STS <=((A >= B_COUNT)or(A > C)); -- will result in “TRUE”

STS <=(std_logic (‘1’, ‘0’, ‘1’) < std_logic(‘0’, ‘1’,’1’));--makes STS “FALSE”

typenew_std_logicis(‘0’, ‘1’, ‘Z’, ‘-‘);

variableA1:new_std_logic:=’1’;

variableA2:new_std_logic:=’Z’;

STS <=(A1 < A2); --will result in “TRUE” since ‘1’ occurs to the left of ‘Z’.

logical operators / And, or, nand, nor, xor, xnor / Can operate on- BIT, BIT Vector, STD_LOGIC, STD_LOGIC_VECTOR, STD_ULOGIC, STD_ULOGIC_VECTOR,

Implement the code for the following circuit

ENTITY example1 IS

PORT (x1,x2,x3 : IN BIT;

f : OUT BIT

);

END example1;

ARCHITECTURE LogicFunc OF example1 IS

BEGIN

f <= (x1 AND x2) OR (NOT x2 AND x3);

END LogicFunc;

Lesson-10VHDL Libraries