Kulliyyah of Engineering

KULLIYYAH OF ENGINEERING

END-OF-SEMESTER EXAMINATION

SEMESTER 1, 2015/2016 SESSION

Programme / : Engineering / Level of Study / : UG 1
Time / : 9.00 am -12.00 pm / Date / : 03/01/2016
Duration / : 3 Hrs
Course Code / : ECE 1312/EECE 1312 / Section(s) / : 1- 5
Course Title / : Electronics

This Question Paper Consists of 12 (Twelve) Printed Pages (Including Cover Page) with
5 (Five) Questions.

INSTRUCTION(S) TO CANDIDATES

DO NOT OPEN UNTIL YOU ARE ASKED TO DO SO

· Total mark of this examination is 100.

· This examination is worth 50 % of the total course assessment.

· Answer ALL QUESTIONS

· Only approved calculator with ‘KoE approved’ sticker is allowed (non-programmable and non-graphical).

· Marks assigned to each problem are listed in the margins.

Any forms of cheating or attempt to cheat is a serious offence which may lead to dismissal.
All electronics gadgets are prohibited in the exam hall / venue.
(e.g. mobile / smart phones, smart watches, and smart glasses)

APPROVED BY:

QUESTION 1 (20 marks)

a) A solar cell is a special type of pn-junction diode. The current equation of a particular solar cell is represented as follows:

ID=5.0×10-13 eVDVT-1-7.7×10-2 (A)

When the cell is irradiated with sunlight and the cell current, ID=0, the voltage VD is referred to as the open circuit voltage, VOC . Similarly, when the cell is irradiated in the sunlight and the cell voltage, VD=0, the current ID at that time is called the short circuit current, ISC. If the cell is operating at room temperature determine the parameters of the solar cell as follows: (4 + 2 marks)

i. Open circuit voltage, VOC

ii. Short circuit current, ISC

b) Consider the circuit shown in Fig. 1(b). The diode cut-in voltage is Vγ=0.7 V. Calculate the output voltage vO and plot it with respect to the input voltage vI in the same time scale over the range of voltages -10 V ≤vI≤ +10 V for VB =5 V.

(4 marks)

Fig. 1(b)

c) A clamper circuit is shown in Fig. 1(c). Write the equation of input-output voltage relation of the circuit. Sketch the output voltage waveform, vO against the time, t, if the input has sinusoidal voltage, vI=6sinωt V and diode cut-in voltage, Vγ=0 V. (4 marks)

Fig. 1(c)

d) In the circuit shown in Fig. 1(d), the power rating of the Zener diode is 4 W.
Let, VI=58 V, Ri=150 Ω, VZ=16 V and the minimum diode current is 15 mA.
(2 + 4 marks)

i. Determine the range of the diode current

ii. Determine the range of the load resistance, RL

Fig. 1(d)

QUESTION 2 (20 marks)

a) Consider the circuit shown in Fig. 2(a). Assume that VCC=2.8 V, β=180 and
VBE on=0.7 V. Design the circuit by finding the values of RB and RC such that
IC=0.12 mA and VCE=1.4 V. (6 marks)

Fig. 2(a)

b) A transistor has current gain, β in the range of 90≤β≤180 and the collector current, IC is in the range of 0.8 mA≤IC≤1.2 mA. What is the possible range of gm and rπ ? Assume that VT=0.026 V. (5 marks)

c) A common collector circuit is shown in Fig. 2(c). Given that b = 100. Assume VBE on=0.7 V.
(3 + 3 + 3 marks)

i. Calculate the value of the DC collector current IC

ii. Sketch the small signal AC equivalent circuit. Assume that VA=∞

iii. Calculate the value of the output resistance RO

Fig. 2(c)

QUESTION 3 (20 marks)

a) A transistor transconductance, gm =50 mA/V and emitter resistance
rπ =1.5 kΩ when it is operating at room temperature. Determine the collector current ICQ and common emitter-current gain β of the transistor. Assume that VT=0.026 V.
(4 marks)

b) A common-emitter amplifier has output voltage -2.4 V when its input voltage is 250 mV. The collector resistance of the amplifier has 1.5 kΩ is changed to 2.5 kΩ, what is the new voltage gain of the amplifier ? Consider that rO=∞.

(5 marks)

c) For the common emitter circuit in Fig. 3(c), the transistor parameters are β=100 and VA=∞. The parameters of the circuit are VBE on=0.7 V, IC=0.5 mA and VCE=3 V. (5 + 2 + 4 marks)

i. Find the value of RE and RC

ii. Draw the small-signal equivalent circuit

iii. Determine the value of the voltage gain, Av=vO/vS

Fig. 3(c)

QUESTION 4 (20 marks)

a) The transistor in the circuit in Fig. 4(a) has parameters VTN=0.8 V and
Kn=0.2 mA/V2. Sketch the output load line and plot the Q-points for VDD=2 V and RD=2 kΩ. Assume the transistor is biased under saturation mode.

(7 marks)

Fig. 4(a)

b) The transistor in Fig. 4(c) has parameters VTN=0.4 V, and Kn=4.8 mA/V2. The parameters of the circuit are ID=0.8 mA and R1||R2=200 kΩ . Assume that the transistor is biased under saturation mode.

(6 + 3 marks)

i. Design the circuit by calculating R1 and R2

ii. Calculate the value of VDS and confirm that the transistor is biased under saturation mode

Fig. 4(c)

c) For an NMOS biased in the saturation region, the parameters are Kn'=0.1 mA/V2, VTN=1.2 V and ID=0.8 mA. Determine the transistor width to length ratio W/L such that gm =1.8 mA/V. (4 marks)

QUESTION 5 (20 marks)

a) The parameters of the common source circuit shown in Fig. 5(a) are VDD=12,
RD=3 kΩ, RS=0.5 kΩ, R1=894 kΩ, R2=347 kΩ and RL=10 kΩ . The transistor parameters are, VTN=1.2 V, Kn=1.5 mA/V2 and λ=0.

(6 + 5 marks)

i. Find the values of ID and VDS

ii. Determine the input resistance, Rin and the small-signal voltage gain, Av

Fig. 5(a)

b) Determine the output voltage vO for vI=3 V for the op-amp circuit shown in
Fig. 5(b). Then, calculate the output current that flows through 5 kΩ resistor.

(4 marks)

Fig. 5(b)

c) For the inverting summing amplifier shown in Fig. 5(c), determine the value of R3 if all the circuit parameters are given as: R1=50 kΩ, R2=40 kΩ, RF=50 kΩ and vO=- 10 V. The inputs to the circuit are, vI1=1 V, vI2=2 V and vI3=0.3 V. (5 marks)

Fig. 5(c)

Some Useful Equations

Equation for pn- junction:

Equations for BJT

Equations for MOSFET

Kn=kn'2WL

End of paper