Instrumentation Development Laboratory

SciFi Tracker

Hardware Design Reference

Author: Peter Orel
Checked by: Gary S. Varner
Approved by: Gary S. Varner / Saturday, October 6, 2018

Table of Contents

1Introduction

2The MPPC photo detector

2.1Modeling the MPPC

2.2Hamamatsu S10362-11-100p MPPC

3Design considerations for the Daughter Card

3.1The preamplifier

3.1.1Differential configuration

3.1.2Singe ended configuration

3.1.3Layout considerations

3.1.4Using the LMH6703

3.2The TargetX interface

3.3DACs

3.4Power Supply

4Design considerations for the Motherboard (IDL_14_36)

4.1Board dimensions and layout

4.2On-board Diagnostics

5Design considerations for the Power board (IDL_14_42)

5.1Intermediate switching PS

5.2Other rails

1Introduction

This document will serve as a repository for all major considerations involving the hardware design.

The goal of this project is to develop a detector box which will track the position of the incident high-energy muons.

The hardware of the detector box can be segmented into three distinct sub-segments:

  1. The Scintillator Bicron DC408 and the MPPC photodiode circuit
  2. The Analog electronics for signal conditioning and acquisition
  3. The digital back-end with the TARGETX digitizer and the SCROD processing board

The following figure shows the block scheme of the detectors box:

2The MPPC photo detector

The MPPC sensor is based on a pixel array of avalanche photodiodes. These photodiodes can be biased with a reverse voltage that is greater that the breakdown voltage of the photodiodes themselves. This is called the Geiger mode of operation. In this mode the electric field at the p-n junction in the photodiode is very strong. When even a single photon gets absorbed and creates an electron/hole pair, the electron gets accelerated by the field and gains sufficient energy to collide with the crystal lattice which generates another electron/hole pair. This pair gets accelerated again and through the same process creates other pairs. This process (Impact ionization) can continue as long as the number of colliding pairs is greater than those being collected in the p and n substrates [1].

The process is of a rather digital nature. It does not depend on the number of photons incident on a single p-n junction. One photon can trigger the process which is then self-sustaining until the bias voltage falls below the breakdown voltage.

There are a few issues around such a design:

  1. Temperature dependence

With higher temperature the vibrations in the lattice become stronger which makes it difficult for the ionization to occur so the temperature should be monitored and the reverse voltage corrected accordingly.

  1. Dark current

The Carriers can be generated by the thermal excitation which makes for false pulses. This again is dependent on the ambient temperature.

2.1Modeling the MPPC

The MPPC pixel is non-linear in nature but can be modeled with the circuit shown in the following figure:

This model can be analyzed in three different states of operation.

  1. PRE-DISCHARGE STATE

The SW switch is opened and the Cdiode is charged

  1. DISCHRAGE STATE

The SW switch close when a photon-electron causes the avalanche. The Cdiode discharges through Rdiode. The pulse current rises until voltage at Cdiode/Rdiode terminal reaches Vbr. After that the avalanche dies out and the SW opens.

  1. RECOVERY STATE

After the SW opens, the Cdiode slowly recharges until the Cdiode/Rbias terminal voltage reaches Vb again. At this point the MPPC is ready to be fired again [3][4].

Figure 1: MPPC equivalent circuit model

2.2Hamamatsu S10362-11-100p MPPC

In our case we are working with a Hamamatsu MPPC chip with part number S10362-11-100p. This chip has 100 pixels connected in parallel. This means that the pulse height depends on the number of pixels discharging at the same time.

Every photodiode has a parameter called the gain which tells us how much charge is generated by one photon-electron normalized in units of elementary charge q=1.602*10-19. This parameter is dependent on temperature and can be stabilized by driving the reverse bias voltage accordingly.

In case of the S10362-11-100p:

G=2.4*106 @70Vr which means that per photon-electron.

On the other hand , where C = 35 pF which means that

  • A gain/temperature dependence curve measurement could be part of the calibration procedure for every MPPC module. This would require driving the box in a temperature chamber or redesign the MPPC module to include temperature stabilization and driving. One elegant solution for this is by using thermoelectric cooling and a simple PI regulator and TEC driver.

By looking at the datasheet information we can assume that the pulse ramp-up time is on the order of a nanosecond. By integrating the charge built-up in time . This is the current pulse amplitude for a single pixel. In the worst case, where all pixels are active together the pulse amplitude would get higher by 100 times. Therefore the dynamic range that needs to be covered is form Ipmin = 0.385 mA to Ipmax = 38.5mA.

Another implication to be considered is the bandwidth which is defined by the rise time to bandwidth approximation. In our case the rise time is on the order of a nanosecond we can approximate the bandwidth to be on the order of 340 MHz. However due to the energy spread in time of the pulse the rise time and consequently the bandwidth requirements can be loosened to about a bandwidth of approximately 100MHz.

The design consideration are based on a specific MPPC part. All of the equations have been taken form the Hamamatsu technical note [2].

3Design considerations for the Daughter Card

3.1The preamplifier

The preamplifier is meant to condition the signal coming from the MPPC array as well as provide the necessary biasing conditions for the MPPC to work in the first place. This can be realized in two different ways: By having a differential configuration where both the bias and termination resistors are equal (balanced input) and by having a single ended configuration where the termination resistor is much lower than the bias resistor and the transmission line is single ended, where the biasing line is for biasing purposes only.

3.1.1Differential configuration

In the differential configuration the sampling circuit is connected to the terminal ends of the MPPC. The figure 2 shows an example of this circuit:

Figure 2: Differential configurator of the pre-amplifier circuit

The voltage pulse amplitude is defined by the both the Rbias and Rterm values which need to be equal in order to have a symmetric pulse response so that the differential configuration works properly since, in our case, its output follows the equation . The pulses are opposite in polarity to each other, figure 3.

Figure 3: Voltage pulses as seen from preamplifier input (AC coupling), Brown is the Anode and Green is the Cathode

This configuration has some advantages and some drawbacks:

Advantages:

  • The signal can be routed differentially which is good for common-mode disturbance rejection
  • Lower gain (factor of 2) required on the pre-amp which is better in terms of GBW product requirement

Drawbacks:

  • The Rterm and Rbias need to be equal which removes the flexibility of setting the proper resistors for the pinching current of the MPPC and at the same time having the desired signal range.
3.1.1.1Simulating the differential configuration.

For simple estimation purposes, the simplest model, which covers the discharge state only, is that of a current source generator in series with the bias and termination resistors. In the discharge mode the photodiode operates in the reverse bias mode, therefore the current source direction is also in the reverse direction.

Figure 4: MPPC model and pulse waveform

The simulation has been done in TINA (Texas Instruments SPICE simulator).

Four operational amplifiers have been evaluated:

  • Texas Instruments, THS4304
  • Texas Instruments, THS3202
  • Texas Instruments, LMH6703
  • Texas Instruments, OPA694

The THS4304 is a voltage feedback amplifier with very high bandwidth but slow slew rate.It is less demanding in terms of feedback components which makes it more stable and more reliable.

The THS3202, LMH6703 and OPA694 have current feedback architectureswhich allows for a higher slew rate which makes it perfect for pulsed signals. However their stability is dependent on feedback component selection.The following table summarizes some key parameters of all four op-amps:

Parameter / THS4304 / THS3202 / LMH6703 / OPA694
Bandwidth / 3 GHz @G=1 / 1.8 GHz @G=1 / 1.8 GHz @G=1 / 1.5 GHz @G=1
Slew rate / 830 V/µs @1V / 5100 V/µs / 4200 V/µs / 1700 V/√Hz
V. Noise / 2.4 nV/√Hz / 1.65 nV/√Hz / 2.3 nV/√Hz / 2.1 nV/√Hz
Quiescent current / 18 mA / 16.8 mA / 11 mA / 6 mA
Input Offset v. / ±4 mV / ±3 mV / ±1.5 mV / ±3 mV

The simulation was done with a pulse rise time of 1ns and a fall time of 20ns.

The following figures show the transient and frequency responses:

Figure 5: Output Transient response for the four op-amps

Figure 6:Output Frequency response for the four op-amps

The bandwidth spans are summarized in the following table:

Part / Low cutoff [kHz] / High cutoff [MHz]
THS4304 / 32.15 / 259.60
THS3202 / 32.10 / 214.00
LMH6703 / 31.78 / 281.00
OPA694 / 31.78 / 148.71

The noise of this configuration is estimated using the formulas given in a Texas instruments application note [5].

The input referred noise for each op-amp and its configuration is given in the following table:

Part / IRN [nV/√Hz] / Integrated [mV]
THS4304 / 3.82 / 0.064
THS3202 / 6.87 / 0.100
LMH6703 / 6.75 / 0.113
OPA694 / 10.32 / 0.173

The signal-to-noise ratio could be estimated at .However considering that the noise flour of the pulse signal is at approximately 2mV. Considering unity gain for the signal noise, the total sum of the noise signal and the pre-amp noise is 2.0121 mV so the SNR would be 19.63 dB.

3.1.2Singe ended configuration

The single ended configuration would be done such that the Rbias and Rterm would be different. The Rbias would be a high value resistor in the region of kΩ, while the Rterm would be a 50Ω resistor. A coplanar transmission wave guide would lead the signal from the MPPC to the pre-amplifier input. Alternatively a balun can be used to transform the signal into a differential signal. The figures 9 and 10 show this configurations.

If VBR=70V, for a 50Ω Rbias the voltage bias should be which for this specific application is 70.0193V. This can be achieved with a DAC that has a LSB lower that half the voltage step which is approximately 10mV. At 5V dynamic range this means a 9-bit DAC or better. However if we look at the MPPC datasheet we can see that the breakdown threshold voltage has temperature dependence of 56 mV/°C which means that we don’t have any margin on the Vbias set-point. This can be solved by driving the Vbias through a regulation loop which follows the temperature change close to the MPPC array. However this can also be problematic since it would essentially be a positive feedback loop, where we increase the Vbias as Vbr increases and Vbr will increase with temperature which also likely to increase if no temperature control is implemented. Also Vbias would eventually saturate.

NOTE: Each MPPC has a specified VBR which is given on the factory test sheet accompanying the MPPC. The example given is just for illustrative purposes.

3.1.3Layout considerations

The layout has been done such that by choosing the assembly variant we can switch from one configuration to the other as seen in the following figures.

Figure 7: Single-ended configuration

Figure 8: Differential configuration

The transmission line has been modeled using Mentor graphics Hyperlinks. When used in the differential configuration the transmission line is differential and has differential impedance of approximately 100Ω On the other hand when used in a single-ended configuration where one of the lines is used for biasing only the single-ended impedance of the termination line is approximately 60Ω.

The ground planes have been cut from underneath the feedback loop and input pins of the amplifier to minimize the parasitic capacitances to ground.

Figure 9: Pre-amplifier layout considerations

3.1.4Using the LMH6703

The LMH6703 is a current feedback amplifier. The stability of the feedback loop is dependent on the value of RF. For this particular package a reasonable value has been obtained by looking at the datasheet figure 29 [6], which is also presented here:

Figure 10: Recommended RF vs Gain

This way a resistor of 590Ω has been chosen. It is to be noted that if the Gain is to be changed, this figure has to be taken into account when choosing the new values for RF and RG.

The stability of a current feedback op-amp is dependent on the feedback resistor. Its internal structure is shown in the following figure:

Figure 11: Current feed-back simplified structure

The transfer function for this model is given as [8]:

As we can see the forward transimpedance has to be high enough that the gain at low frequencies is simply the feedback loop gain 1+Rf/Rg. At high frequencies the Z(s) starts to show by rolling off the gain slope.

For our particular configuration (differential) we essentially need to solve the same equations:

Where

And the input buffer impedance is , where Ri is given to be 30Ω and Ci is 0.8pF.

The forward transimpedance Z(s) has been extrapolated form the spice model and its transfer function is given as:

With a frequency response shown in the following figure:

Figure 12: LMH6703 forward transimpednace frequency response

3.2The TargetX interface

The output of the Preamplifier is fed into a dedicated time domain waveform digitizer IC called the TargetX. The TargeX has 16 channel inputs that are referenced to a pedestal voltage called VPED which can span from 0.4V to any value up to 2.4V. This also determines the input voltage dynamic range since the upper limit is Vcc at 2.5V. In our case VPED has been connected to a LDO sourcing 0.817V. There is also an option of driving this voltage with a DAC.

Input protection has been achieved with schottky diodes with approximately 1ns response time.

The input line geometry has been chosen to accommodate the chosen board stack-up. The transmission line has an impedance of approximately 65Ω.

The analog input of the TargetX can be modeled in similar way to the input of the Labrador AISC [7], as is shown in the following figure:

Figure 13: Approximation of the equivalent input circuit for the TargetX

This circuit has been simulated in ADS. The S11 of the input can be shown in the following figure:

Figure 14: TargetX S11 with 28Ω

As we can see at the frequency of interest the input impedance is approximately 33Ω with an inductive affinity. If we remove the resistor:

Figure 15: TargetX S11 with 1MΩ

The input impedance becomes almost entire inductive. However if we simply terminate then line at the input with a 64.9Ω resistor:

Figure 16: TargetX S11 with input termination

We can see that S11 is very nicely matched resulting in very low reflection. It has to be noted that at higher frequency it presents a capacitive affinity. So for working at higher frequencies this too would have to be compensated.

The digital interface of the TargetX is directly interfaced to the FPGA featuring a 2.5V logic with two dedicated LVDS25 clocks. The LVDS lines are routed differentially and terminated at the TargetX inputs.

3.3DACs

The DACs in this case are used to fine tune the VBR voltage on the MPPC. As has been shown a minimum of a 9bit DAC is necessary to achieve the necessary resolution. We chose the Texas Instruments DAC128S085 which is a 12bit SeriaSPI 8-Channel DAC. It can swing from 0 to 5V and source/sink a continuous current of 10mA per Channel. Its output noise spectral density is 40 nV/√Hz which integrated in our bandwidth of interest is approximately: 0.67mV.

For SW requirementsplease see document:CSciFi DACdriving.docx

3.4Power Supply

For Heat dissipation reasons it has been decided that all of the voltage rails will be generated outside the board. The following table summarizes the voltage rails and their worst case current load:

Voltage [V] / Current [mA] / Power [W]
+2.5 / 280 / 0.7
+4.5 / 169 / 0.76
-4.5 / 169 / 0.76
Σ=2.22

Every daughter card has a worst case power consumption of 2.22W.

4Design considerations for the Motherboard (IDL_14_36)

The motherboard has more mechanical considerations than electrical. The motherboard is meant to be an interconnection plane between SCROD, the daughter-cards and the power supply board.

4.1Board dimensions and layout

The board dimensions are constrained by the scintillator dimensions in one corner and SCROD dimension and runway in the other corner. In comparison with the previous board this version has been reduced by approximately 40% in area.

The board has 8 layers and is 2mm thick in order to reduce the possibility of curving during daughter-card insertion. The layer stack has been chosen so that it has 4 signal layers with reference planes on top and bottom to have good impedance control of the signal lines on the analog side. The reference planes are divided into two pairs of ground and power planes respectively.

The geometry of the lines has been calculated such that the impedance matches the impedance of the lines on the daughter-cads consequently reducing the risk of mismatches and signal distortion.

The layout is done such that the analog signals form the MPPC array and the digital signals form the daughter cards never intersect. The grounding is sliced so that the actual intersection is close to the intersection on the daughter-boards as it can be seen in the following figure:

Figure 17: Ground plane of the motherboard

The analog signal routing between the daughter-cards and the MPPC array has been scrambled so that crosstalk between adjacent channels is minimized.

The estimated highest difference in propagation delay within one group is approximately 0.5ns.

The clocks are routed differentially. The maximum difference in propagation delay between the clocks is approximately 163ps.

4.2On-board Diagnostics

The on-board diagnostic includes:

  • Three temperature sensors
  • Two are located close to the MPPC boards
  • One is locate on the bottom side just above the FPGA of the SCROD board.
  • 4 channel ADC for monitoring the power supply rails (2V5, +5VA, +5VSC, -5VA, HV_BIAS)
  • Auxiliary general purpose TTL compatible clock input/output buffer that is connected to global clock input/output on the SCROD FPGA.

The ADC and temperature sensors are connected to the FPGA via a dedicated I2C interface.