High-Performance FPGA-Controlled Amplifier
Project Plan
May05-28
Client: Teradyne Corporation
Faculty Advisors:
Dr. Chris Chu
Dr. Gary Tuttle
Team Members:
Agus Leonardo, EE
Jimmy Tjoa, EE
Ian Overton, CprE
October 5th, 2004
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Table of Contents
1.0 Introduction
1.1 Abstract 1
1.2 Acknowledgement 1
1.3 Problem Statement 1
1.4 Operating Environment 2
1.5 Intended Users and Uses 2
1.6 Assumptions and Limitations 2
1.7 Expected End Product and Other Deliverables 3
2.0 Proposed Approach and Statement of Work 3
2.1 Proposed Approach 3
2.1.1 Functional Requirements 3
2.1.2 Constraints Considerations 4
2.1.3 Technology Considerations 4
2.1.4 Technical Approach Considerations 4
2.1.5 Testing Requirements Considerations 5
2.1.6 Security Considerations 5
2.1.7 Safety Considerations 5
2.1.8 Intellectual Property Considerations 5
2.1.9 Commercialization Considerations 5
2.1.10 Possible Risks and Risk Management 6
2.1.11 Project Proposed Milestones and Evaluation Criteria 6
2.1.12 Project Tracking Procedures 7
2.2 Statement of Work 7
3.0 Estimated Resource and Schedules 13
3.1 Estimated Resource Requirement 13
3.1.1 Personnel Effort Requirement 13
3.1.2 Advisor Meeting 13
3.1.3 Problem Definition 13
3.1.4 Technology Consideration 13
3.1.5 End Product Design 14
3.1.6 End Product Testing 14
3.1.7 End Product Documentation 14
3.1.8 End Product Demonstration 14
3.1.9 End Product Reporting 14
3.1.10 End Project Review 14
3.1.11 Project Poster 14
3.1.12 Personnel Efforts Requirements Estimate (hours) 15
3.1.13 Other Resource Requirements 15
3.1.14 Estimated Financial Requirements 15
3.1.15 Personal Efforts 16
3.2 Project Schedules 16
3.2.1 Schedules 17
4.0 Closure Materials 17
4.1 Project Team Information 18
4.2 Closing Summary 18
4.3 References 18
List of Figures
Figure 1: Design block diagram 12
Figure 2: Project schedule 17
List of Tables
Table 1: Design specification 3
Table 2: Milestones 6
Table 3: Financial Requirements 15
Table 4: Estimated Efforts 16
Table 5: Team Information 18
List of Definitions
FPGA -- Field programmable gate arrays, a gate array where the logic network can be programmed into the device after its manufacture. An FPGA consists of an array of logic elements, either gates or lookup table RAMs, flip-flops and programmable interconnect wiring.
Analog -- A signal that changes continuously and is not limited to discrete values.
A/D converter -- Analog-to-digital converter is the conversion of an analog signal to a digital sampled signal.
DC offset -- given signal source does not have the correct 0-crossing, and is shifted either up or down from there.
Digital -- A signal that has discrete values, namely one or zero.
D/A converter -- Digital-to-analog converter is the conversion of a digital signal to an analog sampled signal.
DSP -- Digital signal processing is computer manipulation of analog signals (commonly sound or image) which have been converted to digital form.
Dynamic range -- The maximum difference in amplitude between the fundamental and harmonic frequencies (measured in dB).
Fundamental frequency -- The harmonic component of a complex wave that has the lowest frequency and commonly the greatest amplitude.
Harmonics -- Signals that are integer multiples of the fundamental frequency.
High gain -- The ratio of the output amplitude to the input amplitude.
Interfacing -- Providing communication lines between different parts of a system.
Low noise and low distortion -- A low occurrence of undesired signals and interference.
Low pass filter -- A filter that will pass low frequencies up to a point, which is called the corner frequency, after which all frequencies are blocked.
SNR -- signal-to-noise ratio is the ratio of the amplitude of the desired signal to the amplitude of any noise.
Spectrum analyzer -- A computer-based tool that analyzes signals in the frequency domain.
THD -- Total harmonic distortion is the ratio between the power of all harmonic frequencies above the fundamental, to the power of the fundamental frequency.
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1.0 Introduction
Included in this section is the project definition, purpose of the project, and several technologies and intellectual properties that are needed to finish the project.
1.1 Abstract
The purpose of this project is to design a high-performance FPGA-controlled amplifier for Teradyne Corporation. This will constitute Phase IV of an ongoing project for Teradyne. It has to be a characterization of the 100 MHz high-gain, low-noise, and low-distortion amplifier with DC-offset correction and frequency response calibration. The rest of the task will include debugging, tweaking, testing and mid-course corrections from previous projects to meet the design performance goals.
1.2 Acknowledgement
The design team would like to thank Teradyne Corporation for providing Mr. Steven Miller, a knowledgeable and friendly expert who will contribute to the project as well as support to financial.
The design team would also like to thank the faculty advisors – Dr. Chris Chu and Dr. Gary Tuttle who will be guiding the team through the project.
1.3 Problem Statement
There are several problems that are needed to taken care of in this project. The following information will describe the general problems and the possible solutions to the problems.
General problems that will be faced by team design:
· Evaluate and consider accurately the existing phase project.
· DC offset needs to be corrected.
· Better ADC and DAC controller.
· Higher distortion and higher noise.
Possible solutions to the problems:
· Team will meet every week with both advisors and client to discuss the existing phase project.
· Double DC-offset are needed to controller the amplifier more accurately.
· Conduct research on ADC and DAC controller.
· Perform the design simulation in order to make sure everything works perfectly.
1.4 Operating Environment
The system will be used in a climate-controlled laboratory at room temperature with low humidity.
1.5 Intended Users and Uses
The Teradyne Corporation engineers will be the intended users of this system. They plan to use the fully assembled spectrum analyzer to test silicon chips in their laboratories. This design may be used by other companies.
1.6 Assumptions and Limitations
The design team assumes that:
· The end product will not be sale to other companies.
· The frequency operation will be 100 MHz.
· The board fabrication will take up to 6 weeks.
· Necessary equipment will be made available.
· The design should be done in January.
The design team’s limitations are:
Table 1: Design Specifications
Input / TotalInput / Voltage / Available / Max Output / Freq Response / Harmonic
Frequency / Range / Gain Settings / Voltage / Flatness / Distortion / Noise
Range / (Volts) / (dB) / (Volts) / (dB) / (dB) / (nV/rtHz)
DC – 1kHz / +/- 5 volts / 6, 20, 40, 60 / +/- 10 volts / 0.05 dB / < - 105 dB / 1.5 nV/rtHz
> 1kHz - 20 kHz / +/- 5 volts / 6, 20, 40, 60 / +/- 10 volts / 0.05 dB / < - 95 dB / 1.5 nV/rtHz
> 20kHz – 100kHz / +/- 2.5 volts / 6, 20, 40 / +/- 5 volts / 0.10 dB / < -85 dB / 2.5 nV/rtHz
> 100kHz - 1MHz / +/- 2.5 volts / 6, 20, 40 / +/- 5 volts / 0.10 dB / < - 80 dB / 3.5 nV/rtHz
> 1MHz - 10MHz / +/- 2.5 volts / 6, 20, 40 / +/- 5 volts / 0.10 dB / < - 70 dB / 3.5 nV/rtHz
> 10MHz – 20MHz / +/- 2.5 volts / 6, 20 / +/- 5 volts / 0.10 dB / < -65 dB / 3.5 nV/rtHz
> 20MHz – 50MHz / +/- 1.0 volts / 6, 20 / +/- 2.0 volts / 0.10 dB / < -50 dB / 5.0 nV/rtHz
> 50MHz – 100MHz / +/- 1.0 volts / 6, 20 / +/- 2.0 volts / 0.10 dB / < -40 dB / 5.0 nV/rtHz
1.7 Expected End Product and Other Deliverables
The PC based digital spectrum analyzer will be used with Teradyne Corporation’s Integra J750 Enhanced Digital Channel Board, a machine used to test large number of digital chips for other companies. The amplifier produced by the team will serve as a pre-amplifier to the spectrum analyzer. The amplifier will be able to amplify a signal of up to 100MHz. It will have a number of discrete gain settings; programmable by dipswitches on the board. The amplifier will meet noise, distortion, and DC offset voltage specifications.
2.0 Proposed Approach and Statement of Work
This section identifies what approach the team will take to the project and what work must be done for the project to be success. The approach will be determined by what the functional requirement are, what constraints are on the project and what technologies are available to the team.
2.1 Proposed Approach
This section details the approach that the team needed to finish the project.
2.1.1 Functional Requirements
In order to finish the project, several functional requirements have to be considered:
· Wide input frequency range – The amplifier will be able to amplify signals from 0Hz to 100 MHz.
· Programmable gain settings – The amplifier will have programmable gain settings for the specified frequency range.
· DC offset correction – The DC offset correction can be turned on and off.
2.1.2 Constraints Considerations
The design team has to define all the possible constraints and try to eliminate the effect as small as possible.
· Parts constraint – High quality, precision parts are required to obtain the specified design requirements for noise and distortion.
· Bandwidth constraint – Amplification of signals up to 100MHz requires op amps with large bandwidths and near 90˚ phase margin.
· Cost constraint -- Teradyne has promised our team $3000 to complete our project.
2.1.3 Technology Considerations
This design will be involved in both analog and digital technologies since the design team is required to use analog and digital parts to work on the design as well as testing the circuit. The margin error in the circuits design needs to be considered.
2.1.4 Technical Approach Considerations
The team needs to evaluate the previous work done on the design and research if it was the best approach for each subsystem. The rest of the team’s research will be on various textbooks, papers to improve the design, to create a test plan which includes testing techniques and testing programs. In addition, there is a need to research other companies’ websites such as Texas Instrument, Analog Devices and others. Modifications on layout and PCB fabrication will be done using software provided by Teradyne.
2.1.5 Testing Requirements Considerations
Once the design has been fabricated, it will be tested at Iowa State University using the Teradyne Integra J750 Test System. It will involve connecting the input of the chip to Teradyne machine to generate the output signal. Therefore, evaluation on the output can then be made based on the project requirements.
2.1.6 Security Considerations
There should not be any concern about the design being duplicated by other competitors since the design will be presented on the website. Another security consideration will involve testing of the end product, such as the voltage beyond the limited value of 5V. Otherwise, it will burn out the chip.
2.1.7 Safety Considerations
During the test, the team has to make sure that everything is connected right, so that no one will be hurt, ruin the circuit components or break the Teradyne Integra J750 Testing System. In addition, members are required to understand the design completely before being fabricated in order to avoid any failure and waste of money.
2.1.8 Intellectual Property Considerations
Pspice will be used to run the simulation of the design and the Teradyne Integra J750 Testing System will be used to test the end product of the design.
2.1.9 Commercialization Considerations
The design not only needs to consider the intellectual properties, but also needs to be taken into account the price of the circuit components so that it will be cheaper to make and maintain. The circuit should allow for error exceptions, so that it can be more user-friendly and marketable. The circuit shouldn’t be very sensitive to the environment in terms of shaking and impact, so that it will be able to last longer and also makes it more marketable and stable. But all the commercial considerations are decided by Teradyne Corporation.
2.1.10 Possible Risks and Risk Management
Losing a team member will be hard to complete the project; because of this, the requirements will be done for only three people. Therefore, it is better for the team to work cooperatively and efficiently, contributing their best knowledge to the design. Another risk is the time given might be insufficient due to the delay of the fabrication date. In order to prevent this risk, members have to make sure everything should be done on the schedule. Another big risk is to come up with the wrong techniques on improving the design since members are not familiar with the previous design yet. In addition, it will be a waste of money if the end product is working as expected. This will disappoint the client and our department. At the same time, the team will be disgraced.
2.1.11 Project Proposed Milestones and Evaluation Criteria
The project will have several milestones that shown in the table below:
Number / Milestone / Importance1 / Understand previous project / High
2 / Research Results / High
3 / Technology consideration / Medium
4 / Better Design / High
5 / Simulation / Medium
6 / Fabrication / High
7 / Testing / High
Table 2: Milestones
The evaluation criteria will be done at the end of the semester. The evaluation form is given to the advisor and each team members. The evaluation will be based on the ratings as shown below:
(1) Greatly acceded (5) Partially met (2) Acceded (6) Did not meet
(3) Met (7) Did not attempt
(4) Almost met
2.1.12 Project Tracking Procedures
In order to get the project done on the schedule, several tracking procedures need to be considered as follow:
· Microsoft Project will be used to help track the project procedures.
· Weekly email is sent to inform the team members and advisor on the current progress of the project.
· Schedule will be modified every month if required.
· Need to plan at least one week in advance of everything, so that each member keeps reminding of what is needed to do next.