HARPSS-CMOS Process

HARPSS-CMOS Process

By Siavash Pourkamali Anaraki

To fabricate MEMS resonators with CMOS circuits, the first version of HARPSS-CMOS process was developed. This process includes 12 mask layers for the CMOS and 5 mask layers for the MEMS devices. One of the MEMS mask layers is used twice during the process, so 6 photolithography steps are added to the CMOS process to fabricate MEMS devices. 3 lithography steps for MEMS are done before CMOS starts, one in between the CMOS steps and 2 after CMOS is finished. The process flow for HARPSS-CMOS is as below:

Pre-CMOS Steps

1. MEMS Nitride Deposition and Patterning: Since resonators are integrated with circuits, there is no need for large pads that are required for wire-bonding in discrete resonators and pad capacitance limitation is relaxed. Isolation between polysilicon electrodes and the substrate is provided by a layer of LPCVD nitride (thickness ~ 3000A), since pads are small, pad oxide is not needed to decrease the capacitance. In this step LPCVD nitride is deposited and patterned (figure 3.1).

figure 3.1. MEMS nitride after deposition and patterning.

2. Trench Etching: next MEMS step is anisotropic etching of trenches in the ICP that define the shape of resonators and electrodes (figure 3.2).

figure 3.2. Trenches etched to define MEMS resonators.

3. Sacrificial Oxide growth and MEMS Poly deposition: like the existing HARPSS process, trenches are filled with sacrificial oxide and polysilicon, the difference here is that sacrificial oxide is grown, so that oxide will not be formed on top of the nitride pads and there’s no need for an extra step to remove oxide on the pads, also polysilicon can be deposited in one step (no need for poly1, blanket etch and poly2). After oxide growth, it should be doped with boron before poly deposition. Poly is also doped after deposition. Polysilicon on the surface should be etched back so that a thin layer of polysilicon (~0.5 micron) remains on the surface, otherwise the surface will not be flat enough for CMOS photolithography steps.

figure 3.3. Trenches refilled with sacrificial oxide and polysilicon.

5. Removing MEMS Poly and Oxide from the CMOS section: To start the CMOS processing, polysilicon and sacrificial oxide on the CMOS area should be removed, therefore another mask layer is required to cover the MEMS area and etch the polysilicon and oxide on the CMOS section. Wet etching (BOE) should be used for oxide atching, so that the silicon surface will not be damages by the plasma, on the other hand if plasma is used to etch the oxide, alignment marks for the next step that are made of nitride will be etched with the same speed and nothing may be remaining at the end.

figure 3.4. Oxide and poly are removed on the CMOS area.

CMOS PROCESS STARTS HERE

MEMS step between CMOS:

1. Capacitor oxide and Second Poly Deposition: Second poly of CMOS is used for interconnecting MEMS and CMOS, i.e. MEMS poly and CMOS second poly will contact each other to provide electrical connection between the MEMS and CMOS devices. Before second poly deposition, capacitor oxide (800A) is deposited, which covers the MEMS area as well as the CMOS area, therefore to have electrical contact between MEMS poly and CMOS poly, cap oxide should be etched on the MEMS section and a MEMS related mask layer and process step should be added here (figure 3.9). Both wet or dry etch can be used in this step.

figure 3.9. Capacitor oxide is etched on the MEMS section.

After Cap oxide deposition and patterning for MEMS, second poly is deposited (4500 A) and patterned. MEMS poly has not been patterned until this stage and is patterned with the second poly mask. In order to pattern MEMS poly and CMOS second poly, etching time should be increased, so that MEMS poly will also be etched in the area that is not protected by photoresist (figure 3.10). Cap oxide on the CMOS section is also patterned with the same mask as the second poly by BOE.

figure 3.10. CMOS second poly deposition and patterning. MEMS poly is patterned at the same time and with same mask.

POST CMOS STEPS:

1. Release Openings for MEMS: CMOS process is completed now, and complementary MEMS steps should be done. All the passivation and isolation layers should be removed on parts of MEMS area that release openings are going to be formed. Passivation and isolation layers should also be removed all around the MEMS area, so that photoresist that covers the CMOS section during HF release, will be in contact with silicon or polysilicon and HF will not be able to penetrate inside the CMOS section (figure 3.16).

figure 3.16. Removing passivation and isolation layers on the release openings and around MEMS area.

2. Anisotropic and Isotropic Etching of Silicon: Like the usual HARPSS process, to release MEMS structures from the substrate, anisotropic etching of silicon followed by an isotropic etching step are required. Another lithography step using the same mask layer used for etching cap oxide on MEMS area, is done here, so that photoresist will protect the CMOS pads and the area around MEMS on which the passivation and isolation layers have been removed, during etching the release openings (figure 3.17).

figure 3.17. Releasing MEMS devices from the substrate.

3. HF Release: the last step is removing the sacrificial oxide on the MEMS devices, so that they will be released. Photoresist from the last step is still covering the CMOS circuits. Photoresist may not be able to protect the CMOS part during the long HF dip. Using other materials like polymers or metals instead of photoresist is under investigation.

figure 3.18.HF dip for etching CMOS passivation and isolation layers and sacrificial oxide on MEMS devices to release them.

figure 3.19.Photoresist is removed after HF release.