Hardware Design for Realization of Smart Sensor Network
Hardware Design for Realization of Smart Sensor Network
A Proposal to the Army Research Laboratory PEER Program
UMCP Researchers: Professor Martin Peckerar and Professor Neil Goldsman, Dept. of Electrical and Computer Engineering
ARL Researchers: Mr. Luke Currano, Dr. Nibir Dhar and Dr. Madan Dubey
I. Background
Advances in micro-electrical-mechanical systems (MEMS), coupled with new optical devices, present enormous possibilities in the areas of sensors and energy harvesting. Marrying the MEMs and optical sensors (such as IR detectors) with smart electronics can also open new doors in novel machine vision technology such as neuromorphic spectrally agile and retinal sensors. Further, nano-retina sensor concepts could benefit significantly by the combination of new electronic interfaces/protocols that are likely to evolve through this effort. In view of the above thoughts, sensor interface ICs (in the form of ASICs, microcontrollers, DSP, FPGA and/or ADC) can play a vital role in making sensors smarter, and to work effectively in a particular application by amplifying, pre-processing, filtering, and correcting the sensor's signal; eliminating non-linearities and compensating for environmental factors (such as temperature or humidity) that can impair the sensor's measurement accuracy (particularly for PZT MEMs sensors), thereby significantly reducing sensor-signal post-processing requirements, and facilitating the sharing of sensor data with the host back-plane processors.
The Army Research Laboratory has a leading program on the development of new MEMS structures, and IR sensors. These state of the art sensors, actuators and energy harvesters are now ready to be integrated into systems where their benefits can be realized. Using these new devices, we plan to design and fabricate complex distributed smart sensor networks. As a long term goal, we propose to develop a distributed network of small smart sensors that can monitor the environment, communicate with each other, locate sensed objects, perform distributed computations, and reach joint decisions by fusing the data the individual sensors acquire. These sensors could be placed in small UAVs or UGVs for an ad-hoc and adaptive sensor network. Each of the network nodes will include several MEMS and or optical sensors, one or two microprocessors, a transceiver, and perhaps an energy harvester. We expect there to be anywhere from ten to hundreds and perhaps thousands of nodes in the network including UGS. The connectivity of the network will depend on the transmitting power and the distance between nodes.
Figure 1a illustrates the structure of a single node containing one or more MEMS/optical sensors, an analog to digital interface, a processor for interpreting the sensor data and controlling the network, and then a transceiver to share and receive the sensor information with the outside world. Figure 1b illustrates the ad-hoc sensor network. While our long term goals are to develop sophisticated ad-hoc wireless smart sensor networks that may include new sensor modalities that are the results of multidisciplinary technologies such as MEMs/IR, our short term goals are to develop the electronics necessary to control the MEMS sensor devices, extract the sensed information, and where appropriate transform it into digital signals for micro-processing. In the long-term however, we hope to add IR/optical sensors to the network, and develop on-sensor signal processing capabilities that communicate intelligent and relevant information rather than simple images and sensory data.
II. Impact of Proposed Research
We have well developed sensor networks and VLSI design groups at the ECE Dept. of the University of Maryland. Our program in sensor networks is aimed at developing millimeter scale smart sensor nodes called smart dust. With this program, we are designing our own analog and digital integrated circuits and fabricating them through the MOSIS facility. The circuits are for sensing, communication and digital control. This program has a funding level of more than $2 million over the next 4 years. We also have a program on the development of 3-dimensional integrated circuits, which is funded at the $1 million level. Both of these programs fit very well with the goals of our proposed work on electronics for MEMS and Optical Sensor networks with the Army Research Lab. The ARL will be able to benefit significantly from our past experience with these programs by leveraging many of the techniques that have been uncovered. Addition of this project will increase the scope of investigation and lay foundation for next generation of electronics that will enable not only smart sensor network capability, but will also offer circuit concepts for new sensor modalities and new sensor materials/structures such as PZT/ceramic MEMS devices, nanosensor electronic interface and 3D electronics to develop integrated light weight heterogeneous sensors for deploying in small military platforms with smart communication protocols.
III. Research Program: Approach & Milestones
Tasks and Milestones
The focus of our research program in the first year will be to work closely with the MEMS group at ARL to develop state of the art electronics hardware to interface and control their unique sensors and actuators For the MEMS group it is important to develop the electronics to interface their unique devices with the outside world. In particular, we plan to begin our collaboration with the design and development of electronics to help realize the capabilities of MEMS devices including the Shock Sensor and the Piezoelectric Pressure Sensor. The performance and problems of Piezoelectric Ceramic devices are quite different from silicon and other semiconductor devices. Therefore, new device design rules for component architectures will be developed. These issues will be accounted for in our circuit design for piezoelectric sensors which are described below.
All classes of circuits described above will be designed, fabricated, tested and integrated into the sensor/system configuration under development at each phase of the program. Each year, the resulting circuit will be optimized for performance in their chosen application realm.
III. Circuit Development Activity
IIIa. Piezoelectric Pressure Sensor: In a piezoelectric pressure sensor, a piezoelectric crystal is sandwiched between two conducting plates. Upon deformation of the crystal a polarization will occur and a surface charge will be induced on the crystal. The charge can then be transferred to capacitor plates giving rise to free charge separated by a distance, thus creating a voltage source. A major difficulty with this particular capacitive source is that as soon as it begins to provide current, the capacitor discharges, and the output voltage decreases to negligible values. Another difficulty arises from the fact that the piezoelectric material/capacitive structure provides charge that is largely fixed by the piezoelectric coupling coefficient, while at the same time, PZT has a very large dielectric constant. Therefore, while a relatively large capacitance may result, since the charge is fixed, a relatively small voltage may be induced.
The challenge will be to develop electronics which can sense this small charge and/or small voltage. Another important issue is that since the voltage source is capacitive in nature, only voltage amplifiers which draw virtually no current will be appropriate for sensing. Thus, amplifiers will need to be MOSFET based. However, at the same time we have to be careful with respect to noise. Since the signals we are sensing can be relatively small (micro-volt level or below), we must be careful not to add additional noise from the circuit. This is especially important over the bandwidth at which the ARL’s PZT sensors will operate, since at these frequencies, MOS electronics can be sensitive to 1/f (often called flicker) noise. To minimize our noise, while at the same time sense small signals, one needs to design circuits which maximize transconductance, but at the same time minimize input capacitance. However, this will be a challenge since transconductance is proportional to capacitance. We therefore plan to develop an optimization scheme where an optimal balance between low noise generation and high gain (requiring large input capacitance), and low source loading (requiring low input capacitive) can be achieved. To realize this we plan to develop a multi-stage topology with approximately 20dB gain in stage one. Additionally, the amplifier will be bandwidth limited to cover only the operational frequencies of the PZT sensor, and thus reject noise from outside the band of interest. Optimization programs will be developed using the CAD tool MATLAB. Circuits will be designed with the aid of the CAD program Cadence, and submitted to the MOSIS foundry service for fabrication; testing will be performed both at UMCP and ARL laboratories.
IIIb. Analog to Digital Conversion with Range Compression for MEMS: The signals coming from the MEMS devices will be analog. However, it is often convenient to process theses signal digitally. We therefore plan to develop analog-to-digital converters for this purpose. The second circuit employed is a novel “companding” (ADC). This circuit is based on the standard “flash” design, but the ladder resistances are scaled to perform any degree of scale compression. The compander is fairly linear at low signal inputs, but it achieves any level of desired compression at high signal input levels. This creates an enormous increase in dynamic range of the ADC. We have actually fabricated this circuit and have demonstrated its high-speed performance (>100MHz) using the MOSIS AMI 0.5 micron process. The basic architecture and chip layout are shown in Figure 2:
IIIc. Control Circuits for MEMS devices: In addition to ADC circuits, we will also provide control circuits for MEMS devices. For example, the ARL MEMS group is interested in controlling their MEMS Shock Sensor. This sensor closes a circuit when a critical acceleration is reached. To detect the closed circuit, we will apply a voltage to the accelerometer terminal which in turn will source a signal to a transimpedance amplifier which will provide a trigger signal to a comparator threshold detector circuit. This comparator will then activate a signal to a current source which will provide the energy to the thermal actuator to release the latch.
Budget:
Graduate Research Assistant focusing on Piezoelectric Circuits: 45K
½ Graduate Research Assistant focusing on ADC Circuits 23K
Faculty salary guiding overall program:27K
Total:95K
MARTIN PECKERAR
Dr. Peckerar received a B.S. from Stony Brook University, and his M.S. and Ph.D. degrees from the University of Maryland. In 1976 he joined the Westinghouse Advanced Technology Laboratory where led a group working in advanced MOS process development. At Westinghouse, he developed the deep-depletion CCD for x-ray and for IR imaging. In 1981, he became head of the Nanoelectronics Processing Facility at the Naval Research Laboratory (NRL) and, subsequently, head of the Surface and Interface Sciences Branch. Here, he developed devices for deep-UV imaging and was co-inventor of the laser-plasma source for x-ray lithography. This source is the primary radiation source used by the Intel-led EUV consortium. He has been Principle Navy Technical Officer on the DARPA Advanced Lithography Program (1989-2003). He was also assigned the role of US Navy consultant to the State Department on issues relating to strategic arms control for electronic weapons systems. Dr. Peckerar is now Professor of Microelectronic Engineering at the University of Maryland.
His current research continues to be centered in the analog and mixed signal design. In particular, he is active in incorporating new materials systems and processes into the system-on-a-chip tool-set. He has developed algorithms for e-beam proximity control, which are essential for e-beam mask manufacture. He was the co-inventor of the polysiloxane self-assembled film imaging process. He has also developed instruments for improvement of e-beam pattern placement using local-fiducial networks. He is also an expert in the area of imaging system technology. Among his achievements in this area is the development of a maximum-entropy image reconstruction chip. This chip represented the first application of entropy regularization to integrated circuit signal processing. He has developed fast-Fourier chips based on neural net principles and a tomographic imager chip (also based on maximum entropy principles). Most recently, he is developing “super-capacitor” power sources for distributed ad hoc sensor arrays. He is co-author of the textbook Electronic Materials: Science And Technology. editor of the book Synthetic Microstructures in Biological Research, and co-author of the book The Korean Electronics Industry. Dr. Peckerar was elected a Fellow of the IEEE in 1993.
NEIL GOLDSMAN
Summary of Activities in VLSI Design
Neil Goldsman is a professor in the Electrical and Computer Engineering Department at the University of Maryland at College Park, where he directs the Mixed Signal VLSI Design Laboratory and the Semiconductor Simulation Laboratory. He received his Ph.D. with a major in Electrical Engineering and a minor in Applied Physics from Cornell University. He has more than 120 publications, and is the principal investigator on research grants and contracts that total more than $1million for current fiscal year.
Dr. Goldsman regularly teaches VLSI design, and has introduced into the University of Maryland curriculum two new courses on the subject: ENEE408D (Mixed Signal VLSI Design, a senior capstone class) and ENEE614 (Radio Frequency VLSI Design, a second year graduate class). He also introduced ENEE306 (Electronics Circuits Design Lab) and wrote the text for the course.
Dr. Goldsman currently has two sponsored research programs in the area of mixed signal VLSI design. One program is on developing the electronics to achieve 3-dimensional integrated circuits; the other program is to develop the hardware and integrated circuits for distributed millimeter scale smart sensor nodes for distributed sensing and computational networks. In the course of these programs, Goldsman’s research group has designed and fabricated more than twenty five custom integrated circuits. The design and layout is performed in the laboratory, which ultimately yields a GDS2 file, which contains a blue-print of the integrated circuit. This file is then submitted to the MOSIS facility for IC fabrication. Once fabricated, the chip is sent back to Dr. Goldsman’s lab for testing. Various types of IC’s have been designed and fabricated. Chips for smart sensor networks have focused on communication IC’s including voltage controlled oscillators (VCO) and phase-locked loops. Goldsman’s smart sensor network activities also involve energy harvesting using ambient electromagnetic waves. In this effort, his group is developing VLSI inductors and transformers for energy storage circuits. Goldsman’s group has also developed numerous IC’s for use in 3D integrated circuits. In one particular circuit, his group was chosen to contribute a design for a unique 3D integration fabrication run that was performed at MIT Lincoln Labs. This circuit contained 3 layers. On the top layer, we design a system of photodiodes for energy harvesting. The next layer contained a large system of storage capacitors, which worked to power the VCO circuit implemented on the bottom level. Other interesting circuits that were recently designed and fabricated under Goldsman’s supervision include temperature sensor arrays, and frequency counters for use as on-chip instrumentation circuitry in the 3D-integration program. Dr. Goldsman’s publications in the area of VLSI include papers on optimized on-chip inductors (see for example, Bai, Dilli, Goldsman, Metze, ISDRS 2003), and on the heat generation in integrated circuits (see for example, Akturk, Goldsman, Metze, Solid State Electronics, 2005). Attached is a list of the IC’s that have been designed and fabricated under the direction of Dr. Goldsman in the last several years.
Integrated Circuits Designed and Fabricated Under Supervision of Neil Goldsman
No. MOSIS MOSISDesigner(s), DateDescription
Proj. No. Fab.ID
------
1. 65008T26BDFYun, Goldsman, Jun'02Monolithic FSK
Transmitter
2. 65759T2AKAVYun, Goldsman, Oct'02
3. 65760T2AKBJYun, Goldsman, Oct'02
4. 65761T2AKBNYun, Goldsman, Oct'02
5. 65762T2AKBDYun, Goldsman, Oct'02Substrate noise
coupling analysis
6. 66962T33AACYun, Goldsman, Apr'03Substrate noise
coupling analysis
7. 66963T33AADYun, Goldsman, Apr'03Inductors/substrate
noise coupling analysis
8. 64639T26ZAYDilli, Goldsman, Jun'02Internal/external ring
osc., counters
(Measurements on the loading effectsof off-chip connections and
packaging).
9. 65046T26BBJDilli, Goldsman, Jun'02Internal/external ring
osc, counters
(Measurements on the loading effectsof off-chip connections and
packaging; delay measurement structures).
10. 65765T2AKASDilli, Goldsman, Oct'02 Three dimensional
ring osc., counters
(Chip designed for post-processing to create three-dimensionally
integrated ring oscillators and counters; measurements on the loading
effects of three-dimensional interchip vias.)
11. 68785T3AJALDilli, Goldsman, Oct'03 On-chip inductor
structures
12. 68786T3AJAMDilli, Goldsman, Oct'03 On-chip
digital/analog
coupling structures
(Chips designed for RF-probe station measurements: On-chip
digital and analog and RF structures, substrate coupling, digital
noise.)
13. 68865T3AJBVAkturk, Parker,Heaters and
Goldsman Oct'03temperature sensors
14. 68866T3AJCDAkturk, Parker,Heaters and
Goldsman Oct'03temperature sensors
15. 68893T3CUCFAkturk, Parker,Heaters and
Goldsman Oct'03temperature sensors
(Chips designed with on-chip heating elements like switching
digital circuits or polysilicon resistors and diodes as temperature
sensors, to study chip heating.)
16. 70241T46TAGDilli, Goldsman May'04Inductors
17. 70242T46TAFDilli, Goldsman May'04Inductors
(Inductor structures on different substrates; de-embedding
structures; for measurements on the substrate doping effect on