INFN-FE, Angelo Cotta Ramusino 2013-10-14

GTK_DataReceiver module description

last modified 2013-10-24

entity GTK_DataReceiver is

generic (

HITCOUNT_MAX_INDEX : integer := 12);

port(

rx_datain: IN STD_LOGIC_VECTOR(15 DOWNTO 0);

rx_ctrldetect: IN STD_LOGIC_VECTOR(1 DOWNTO 0);

rx_clkout: IN STD_LOGIC;

rx_freqlocked: IN STD_LOGIC_VECTOR (0 DOWNTO 0);

rx_pll_locked: IN STD_LOGIC_VECTOR (0 DOWNTO 0);

reset: IN STD_LOGIC;

par_rx_data_out: OUT STD_LOGIC_VECTOR(47 DOWNTO 0);

FIFOwr_out: OUT STD_LOGIC;

hit_count_out: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);

CRC_calc_on_rcvd_frame:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);

crcbad_from_trueCRCchkr: OUT STD_LOGIC;

crcvalid_from_trueCRCchkr: OUT STD_LOGIC;

o_total_frame_counter: out std_logic_vector (31 downto 0);

o_error_frame_counter: out std_logic_vector (31 downto 0);

o_good_frame_counter: out std_logic_vector (31 downto 0);

o_error_flag: out std_logic

);

end GTK_DataReceiver;

  • Clock domain(s): “rx_clkout”(160,32MHz)

The operation of this module is synchronous to the “rx_clkout” clock signal originating from the XCVR module (at the top level) in the synthesis-targeted design hierarchy or from the testbench in the simulation-only design).

  • Overview:

The module receives the 16bit words coming from the 3.2Gbps de-serializer, formats them into 48bit words according to the TDCpix format and provides the “FIFOwr_out” signal to store them into the derandomizer input FIFO instantiated at the higher level of the design hierarcy.The “GTK_DataReceiver” recognizes the framing words (TWO, IN THIS DEBUG DESIGN) and calculates the CRC on the received data until and including the first framing word; the calculated CRC is compared to the value of the CRC field of the second frame word. The “GTK_DataReceiver” flags good data frames by issuing the combination crcvalid_from_trueCRCchk=’1’ and crcbad_from_trueCRCchkr=’0’ for one clock cycle, while the combination crcvalid_from_trueCRCchk=’1’ and crcbad_from_trueCRCchkr=’1’ flags a good data frame.The “GTK_DataReceiver” also outputs diagnostic informations such as the CRC error flag, the total count of received frames, the count of frames with matching CRC and the count of frames with a mismatch between calculated and received CRCs.

Please note that in the “test_assembly_oct_slave_ta1”module the 16-bit wide output data port of the “GTK_DataGenerator” is directly connected to the input data port of the “GTK_DataReceiver” via the testbench “test_assembly_oct_slave_ta1_tb”.

  • Detailed description:

The module instantiates a CRC generator for 16 bit words which calculates theCRC-16-CCITT value on the incoming packet up to and including thefirst trailer word. The “pace_maker” state machine starts the CRC calculator when, after coming out of reset, it detects the first data (= non-K) code output by the deserializer. The “pace_maker” state machine is reset when the high speed serial receiver is not in “lock-to-data” mode OR when the GTK_DataReceiver module’s “reset” input is activated: in the debug implementation the “reset” is controlled by the “ExtraRxRst_from_button” signal at the top level.

Fig.1 screenshot from functional simulation of “sim_test_assembly_oct_slave_ta1”(exploiting an abstract model for the UNIPHY controller)

The timing diagram above shows that the CRC generator’s operation is controlled by the “reset_n”, “datavalid”, “startofpacket” and “endofpacket”. The “datavalid” is high for all data words except for the second trailer. The “endofpacket” signal is true for one clock period at the end of the first trailer word received. The “startofpacket” signal is set for one clock period with the onset of the “datavalid” following an “endofpacket”  the very first frame received in this test design DOES NOT GET a “startofpacket” signal but since the CRC generator was in this case cleared by the initial reset it correctly computes the CRC anyway. The CRC generator’s “reset_n” signal is activated at the beginning and, at any rate, it is also activated for one clock pulse after the reception of the second trailer word.

Please note thataccording to the TDCpix manual there no CRC is trasmitted with the frame word so some of the details described here are important only to understand this debug setup.