CSE 378 Computer Hardware Design D. Hanna
Fall 2006 R. E. Haskell
Lab 3 – Signed and Unsigned Comparator
Part A:
Create a project in Active HDL called Lab3 and add the source file comp.vhd for the n-bit signed and unsigned comparator described by the VHDL program shown in slides D4.3:10-11. Generate and print out the waveform shown in slide D4.3:12. Note that in order to do this, you will need to change generic(width:positive); to generic(width:positive := 4); so that there is a default bus width.
Part B:
1. Create a Design called Lab3x using Aldec Active-HDL within the Lab3 directory created in Part A. Add the files comp.vhd and mux2g.vhd (from Lab 1) to the project. You can use the same LAB3 workspace by selecting File à New à Design instead of creating an entirely new workspace. Also, when you add an existing file to the Design, notice that you can make a local copy of the file by checking the make a local copy check box when you browse for the file. If you don’t check this box, Aldec will link the original copy to your current Design. Either way will work, it depends on whether or not you want your files located in one place (with multiple copies for different Designs) or scattered in different directories (with one copy only and multiple Designs using it).
2. Create and add to the Design the file, Lab3.vhd, using the VHDL component wizard that will implement the top-level design shown in Fig. 1. Write and add to the project a VHDL module called GEL.vhd using the VHDL component wizard that will display a G, L, or E on the right-most 7-segment display depending on whether the output of the multiplexer is GT, LT, or EQ. The other three 7-segment displays and the decimal points should be blank. Connect the mux select line, sel, to pushbutton BTN0. Connect the switches to the corresponding LEDs. Create and add an appropriate Lab3.ucf file to the project to define all pin numbers. Remember to include the component declarations for comp, mux2g, and GEL before the begin of the architecture.
Figure 1 Top-level design
A Few Hints:
· The MUX bus width is 3 while the comparator bus width is 4
· You will need to set the LD(7 downto 0) signals to the SW(7 downto 0) signals
· Don’t forget the Anode signals AN(3 downto 0), they are not included in Figure 1 J
3. Simulate your design to make sure that it is operating correctly. A suggested test case would be to apply an A5 to the switches and a clock stimluator to BTN0. A second test case would be to apply an AA to the switches with the clock on BTN0.
4. Synthesize and implement your design. Don’t forget to create the .ucf file using PACE and to select the option to use that file in the Implementation Options. Also, remember to create a .bit file to download to the board. After you have finished implementing your design, follow the instructions in Appendix 3.1 included with this Lab exercise to explore the logic as Xilinx has synthesized and implemented it on the Spartan 3 FPGA. Print a copy of one of the SLICE diagrams using File à Print from the FPGA Editor.
5. Download the .bit file to the Spartan 3 board. Demonstate the operation of the comparator to your lab instructor and get his signature on a copy of Lab3.vhd.
6. Hand in the listings of your files Lab3.vhd and GEL.vhd, a printout of the simulation waveform generated in Part A, and a printout of one of the Slice diagrams from (4).
APPENDIX 3.1
After you have implemented the design on the FPGA, the FPGA editor can be used to view the contents of the FPGA according to how the software has synthesized and implemented your design.
As a first step towards considering how the design was implemented, let’s take a look at the Implementation Report to see how much of the FPGA was utilized.
A Notepad containing the report will appear on the screen. Scroll down to the Device Utilization Summary.
This shows that 28 out of the 173 available input/output buffers where used (16%) to support the designs inputs and outputs. Also, it shows that 3 Slices were used to implement the design’s logic. That is, only 3 out of the 1,920 Slices on the FPGA were used (only 1%). Since this was a simple design, that’s not surprising.
Now that we know how much of the FPGA was utilized, we can use the FPGA Editor to take a look at these 3 Slices and see what logic is contained within them to implement our design. Click on the Design Flow tab to return to the main design flow menu.
Notice on the map of the FPGA a small red dot appears on the right side of the FPGA. This is physically where the pin that AN<0> is connected to is located.
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When the design was synthesized, the logic was reduced to a minimal set of logic equations. This turned out to require three slices. You should recognize the components in this viewer as those presented in class when looking “inside an FPGA Slice on the Spartan 3”. Close the Slice viewer.
Scroll through the list of components in the Component List. Notice that there are three of type SLICE and the rest are IOBs. The larger the design, the more slices it will require. Therefore, there will be significantly more SLICE components listed in this box.
The comparator without any other components (i.e. the MUX, GEL Display, etc…) synthesizes to logic equations that directly match those derived using K-Maps.
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