EE 501, Fall 2013,Design Project 1

Fully Differential Multi-StageCMOS Op Amp Design

Objectives:

  1. Understand the relationships between op amp specifications and biasing, sizing, and layout, and relationships among various specifications.
  2. Understand fundamental limitations, constraints, trade-offs, and optimization issues in multistage CMOS op amp design
  3. Understand stability, compensation, and common mode feedback.
  4. Gain experience in designing and simulating Op Amps and supporting circuits
  5. Gain experience in floor planning, matching layout, DRC/LVS checking, post layout simulation, and taping out for fabrication.

Tasks:

Design afully differential multi stage CMOS Op Amp, including

  1. Analyze the design specifications and make an educated selection of an Op Amp architecture that can support attainment of desired specs.(20%)
  2. Analyze the selected architecture, including
  3. Large signal analysis to reveal constraints to ensure all transistors in their intended operation region.(10%)
  4. Small signal analysis to provide equations and/or simulated curvesrelatingvarious op amp specifications to biasing/sizing.(10%)
  5. Based on the analysis results, provide a design procedure enabling the sizing and biasing of all transistors. This can be based on either equations, or based on empirical curves, or simulation benches, or combinations.(20%)
  6. Explain and design a suitable DM compensation network, a CMFB circuit, and all the biasing circuits from an off-chip reference current source.(20%)
  7. Provide test bench circuits (with your entire op amp represented as a triangle with 8 pins mentions below) for schematic simulationof all op amp and evaluation of all design specifications.(10%)
  8. Provide simulation results of amplifier performance at nominal(and various process corners for key parameters) via graphs and table, with suitable captions as well as description and conclusion in the main text. (10%)

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  1. Floor planning with justifications, overall layout, and detailed layout of match-critical components with description and explanations. (10%)
  2. Proof of DRC and LVS, and post layout simulation results showing performance at nominal (and various corners, optional). (10%)

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  1. Optional: Monte Carlo simulation with process variations and voltage supply variations, and simulation at low temperature and at high temperature for a few key parameters. (5%)

Architecture constraints:

  1. Fully differential structures for which CMFB is necessary
  2. At least two stages for which appropriate compensation (for both differential loop and common mode loop stability) is a necessity to ensure closed-loop stability.
  3. You may have additional pins, but the following 8 are needed:
  4. Vip, Vin, Vo+, Vo-, VDD, VSS, IRef, and VocRef.
  5. The VocRef pin is for the user of the chip to specify/adjust a desired common mode voltage for the op amp output. If it is set by a voltage source, your op amp should enforce it. If it is left floating, your op amp should set its own VocRef to be near the center of the output swing range.
  6. The VDD andVSSare always set by the user to fixed voltage sources. IREFis always set by the user to a fixed current source. But there may be power line noise that causes these sources to have small signal variation components.

Process constraints:

  1. To facilitate free fabrication through MOSIS, you are to use ON0.5um from MOSIS
  2. If you do not plan to fabricate, you may choose to use a different process, such as the TSMC 0.18um. But you need to sign NDA to get access to true process parameters. There is a “generic” 0.18 um process openly available in the library.
  3. Supply voltages used in simulation should be commensurate with process selection.

Op Amp Basic Specification Targets:

  1. Power supply variation tolerance: +– 20%.
  2. Total power consumption of chip:<=2 mA * (Vdd-Vss)
  3. Output driving capability: a capacitive load of 2 pf on each output. This is in addition to the parasitic capacitors at the output node, but includes everything that is connected to the output node from outside the op amp.
  4. Vout swing range on each side:, >=80% of Vdd–Vss
  5. Input common mode range: >= 50%, should target >=60% of Vdd–Vss.
  6. Gain-bandwidth product: >= 50 MHz. This one needs to be checked for various input common mode voltages, various VocRef values, and possibly various corners.
  7. DM DC gain: >= 90dB. This is another parameter that needs to be checked for various conditions.
  8. Maximum percentage overshoot in small size step response: <= 15%. You can test at various feedback gains, but must include gain of -1.
  9. Feedback network could be capacitive or resistive or a combination. Provide justification for your choices. Use appropriate component values and justify your choice.
  10. Should test at a few different conditions involving Vicm and/or corners.
  11. Phase margin at unity gain frequency of A. This should be tested at multiple different conditions.
  12. Systematic differential offset voltage: should be zero in schematic simulation, and should be <=15 mV with process variations.
  13. Slew rate: >= 100 V/s at each side, >=200V/s for differential output.
  14. Settling time in 0.2 V step responsein gain of -1 feedback: <= 50 ns for +– 0.1% settling tolerance.

Other Specifications to consider:

  1. CMFB loop stability: phase margin >= 55 degrees
  2. CMFB loop unity gain bandwidth: about 5 to 10 times lower than differential mode UGF.
  3. CMRR: >= 60 dB at DC
  4. PSRR: >= 60 dB at DC
  5. Input referred noise voltage: in nV/sqrt(Hz), should consider in design and should report, roughly it should be less than the thermal noise of a 50KΩ resistor.
  6. Gain linearity: in terms of gain variation over Vout swing range, should simulate and report, but no specific requirement imposed.
  7. AC response linearity in gain of -1 feedback configuration, should simulate and report, but no specific requirement imposed:
  8. THD vs frequency and/or vs output signal magnitude
  9. SFDR vs frequency and/or vs output signal magnitude

Suggested choices:

  1. Two stages, first stage cascode or folded cascode, 2nd stage common source
  2. A possible sequence of schematic design steps could be: architecture and current budget, second stage CS, input pair, cascoding, compensation, CMFB, bias circuits.
  3. In each step use VCVS for the components not designed yet
  4. Always place high gain amplifier in feedback for sizing/tuning/biasing
  5. Use cascoded tail current source
  6. Use higher VEB’s and/or cascoding for current setting transistors
  7. Use lower VEBs for transistors requiring large gm
  8. Use more current in second stage than in first
  9. Start with just enough second stage current for SR
  10. Try to achieve a large gm for second stage
  11. For compensation, use R/C, not just C
  12. CMFB: as in lab; need to make sure that Voc stability and input CM range of CMFB circuit are appropriately taken care of.
  13. Biasing circuit: accommodate Vicm variation, as discussed in class
  14. Floor planning: symmetric layout, place match sensitive pairs on thermal symmetry line, use differential signal routing, place match-critical pair far away from disturbance sources, plan for enough gaps for well and substrate ties
  15. Layout: input pair high order common centroid matching pattern

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