Module – 3

  1. What do you mean by memory hierarchy? The three characteristics of memory: cost, capacity and access time are related to each other as one goes down the memory hierarchy.
  2. Explain the working principle of a binary storage cell.
  3. What are the key properties of semi-conductor memory
  4. What are the differences between DRAM and SRAM.
  5. Why periodic refreshing is needed for DRAM memory module.
  6. What is memory access time.
  7. Give a block diagram for a 250k x 16 memory module using 64k x 1.
  8. Why cache memory is used in a computer system.
  9. Can a RAM (organized as 4k byte) be need to realize 32k bit RAM.
  10. A large cache can definitely improve system performance, but is not implemented due to economic considerations. What is your opinion on this.
  11. What do you mean by dirty bit and what is the use of dirty bit.
  12. Why mapping function is needed when we use cache memory in the computer system
  13. Explain the LRU replacement algorithm.
  14. A block set associative cache consists of a total of 128 blocks. These are divided into set consisting of 4 blocks in each set. The main memory contains 8192 blocks. Each block contains 256 words.
  15. How many bits are there in a main memory address.
  16. How many bits are there in each of the TAG, SET and WORD fields.
  17. What are the differences among direct mapping, associative mapping and set-associative mapping.
  18. Consider a computer with the following characteristics total of 1Mbyte of main memory, the word size is 1byte, block size is 16 bytes and cache size is 64k bytes.
  19. For the main memory address D0010, 12345, CDABF and F00FF, give the corresponding tag, cache, line address and word offsets for a direct-mapped cache.
  20. Give any two main memory addresses with different tags that map to the same cache slot for a direct mapped cache.
  21. For the main memory address of F00FF and CDABF, give the corresponding tag and offset values for a fully associative cache.
  22. For the main memory address of F00FF and CDABF, give the corresponding tab, cache set and offset values fore a four-way set associative cache.
  1. What is the purpose of swapping
  2. If a process may be dynamically assigned to different locations in main memory, what is the implication for the addressing mechanism.
  3. Is it necessary for all the pages of a process to be in main memory while the process is executing.
  4. Must the pages of a process in main memory be contiguous?
  5. What is the purpose of a translation look aside buffer.
  6. Suggest reasons why the page size in a virtual memory system should be neither very small nor very big.
  7. What are the disadvantages of using variable size partitions.
  8. What is page table. How page table is used to translate the virtual address to physical address of memory.
  9. Consider a paged logical address space (composed of 64 pages of 4k bytes each) mapped into a 2Mbyte physical memory space.
  10. What is the format of the processor’s logical address
  11. What is the length of the page table.
  12. What is the length of the inverted page table.
  13. What is the effect on the page table if the physical memory space is reduced by half.

Module – 4

  1. What are the typical elements of a machine instruction?
  1. What are the different categories of instructions?
  1. Why are transfer of control instructions needed?
  1. If an instruction contains four addresses, what might be the purpose of each address?
  1. List and explain the important design issues for instruction set design.
  1. What are the different types of operands may present in an instruction.
  1. Briefly explain the following addressing modes- immediate addressing direct addressing, indirect addressing displacement addressing and relative addressing.
  1. What is indexed addressing and what is the advantage of auto indexing?
  1. What are the advantages and disadvantages of using a variable-length instruction format?
  1. An address field of an instruction contains decimal value 250. Where is the corresponding operand located for –
  1. Immediate addressing
  2. Direct addressing
  3. Indirect addressing
  4. Register addressing
  5. Register indirect addressing

Module – 5

  1. What are the major components of CPU?
  2. What is the overall function of a processor’s control unit?
  3. Provide a typical list of the inputs and outputs of a control unit.
  4. What are the basic tasks that must be performed by a CPU?
  5. Why registers are used in CPU?
  6. Explain the use of the following registers –
  7. Program counter
  8. Instruction register
  9. Memory address register
  10. Memory buffer register
  1. What do you mean by flag bits. Explain the use of the following flags- sign, zero, carry, overflow and equal.
  2. What are the main two phases of instruction execution.
  3. Give and explain the instruction cycle state diagram.
  4. Explain the tasks that can be performed during fetch phase of an instruction execution.
  5. Consider the single bus organization of the CPU that is explained in the lecture note. Write the sequence of control steps required for each of the following instructions-
  6. Subtract the number NUM from register R1
  7. Subtract contents of memory location NUM from register R1
  8. Subtract contents of memory location whose address is at memory location NUM from register R1
  1. What is the use of control signal Memory Function Complete(MFC) and Wait for Memory Function Complete(WMFC).
  2. Give the organization of control unit and explain each components.
  3. What is the relationship between instructions and micro-operation
  4. What do you mean by horizontal and vertical organization of micro instruction
  5. Why micro-program counter(MPC) is needed in micro-programmed controlled architecture.
  6. Explain the following sequencing techniques for micro-program. Two address fields, single address fields and variable format.
  7. What are the advantages and disadvantages of hardwired and micro-programmed control? Why is micro-programmed control becoming increasingly more popular.

Module – 6

  1. What are the functions of an I/O module.
  2. Briefly explain the techniques for performing I/O.
  3. What are the differences between memory mapped I/O and isolated I/O.
  4. Why we use and I/O module to connect the peripheral devices to the CPU.
  5. When a device interrupt occurs, how does the processor determine which device issued the interrupt?
  6. How an interrupt mechanism works- explain briefly.
  7. Explain the concept of daisy chain mechanism for device identification.
  8. What are the advantages of using DMA.
  9. Explain the DMA module and its function.
  10. In most computers, interrupts are not acknowledged until the end of execution of the current machine instructions. Consider the possibility of suspending operation of the CPU in the middle of execution of an instruction in order to acknowledge an interrupt. Discuss the difficulties that may arise.

Module – 7

  1. What is synchronous bus and asynchronous bus.
  2. What is the advantages of using multiple clock in synchronous bus.
  3. Explain the hand shake control of data transfer for asynchronous bus.
  4. How are the data written onto a magnetic disk.
  5. How are the data read from a magnetic disk.
  6. Define track, cylinder and sector.
  7. Define the term seek time, rotational delay and access time.
  8. What is zone and sector of a disk and how they differ.
  9. Explain the fixed head and movable head disk unit.
  10. What is the format of a disk address.
  11. What are the information that need to be exchanged between the processor and the disk controller during data transfer.
  12. What do you mean by cylinder. Why it is advantageous to access the data cylinder wise.

Module – 8

  1. What are the distinguishing characteristics of RISC organization.
  2. Briefly explain the basic approaches used to minimize register-memory operations on RISC machines.
  3. Give some reasons for shifting the paradigm from CISC to RISC.
  4. Explain the concept of register window to handle the procedure calls.
  5. If a circular register buffer is used to handle local variables for nested procedures, describe the approaches for handling global variables.
  6. Explain the concept of graph coloring to optimize the register uses.
  7. What are the differences of using large register file and cache memory.

Module – 9

  1. Explain the concept of instruction pipeline.
  2. How do you evaluate the performance enhancement of a pipeline processor with d number of phases with respect to a processor without pipeline.
  3. Why is a two stage instruction pipeline unlikely to cut the instruction cycle time in half, compared with the use of no pipeline.
  4. What is branch penalty?
  5. What do you mean by static branch strategies and dynamic branch strategies to deal with branches in pipeline processor.
  6. What is a branch history table and how it is used to deal with branches.
  7. Explain the concept of delayed branching technique.
  8. What is a loop buffer. How loop buffer is used to handle the branching in pipeline processor.

Module – 10

  1. What do you mean by parallel processing?
  2. What are the classification of systems with parallel processing capabilities given by Flynn.
  3. What are the basic characteristics of symmetric multiprocessor(SMP).
  4. What do you mean by tightly coupled multiprocessor.
  5. What are the basic features of time shared bus.
  6. What is multi-port memory and how its is used in multiprocessor systems.
  7. What are the differences among UMA, NUMA and CC-NUMA.
  8. Explain the concept of crossbar network.
  9. What is multistage network?
  10. Why the cache coherence problem is present in multiprocessor system.
  11. What is the difference between software and hardware cache coherent schemes?
  12. What are the write back and write through policies.
  13. Explain the concept of snoopy protocol.
  14. What is write invalidate and write update.

Module – 11

  1. What are the flag bits available in 8085 and 8086 microprocessor?
  2. What is the register organization of 8085 and 8086 microprocessor?
  3. What is the size of memory modules that can be connected to 8085 and 8086 microprocessor?
  4. How the data bus and address bus are multiplexed in 8085 and 8086 microprocessor?
  5. How the 20bit address for memory in 8086 microprocessor is generated from the content of a 16-bit register?
  6. What are the instruction formats of 8085 and 8086 microprocessor?
  7. Find out the largest number from an unordered array of fifty 8-bit numbers stored sequentially in memory location starting from 1000H. Write a machine level program for 8085 microprocessor.
  8. Find out the largest number from an unordered array of fifty 8-bit numbers stored sequentially in the memory location starting at offset 0100H in the data segments 5000H. Write a machine level program for 8086 microprocessor.
  9. How an 8-bit and 16-bit data are handled in 8086 microprocessor.
  10. Write a program for 8086 microprocessor for the addition of a series of one hundred 8-bit numbers.