Ex 3Digital Circuits and Systems

EX3: Designing a UART

EX 3DIGITAL CIRCUITS AND SYSTEMS

Designing a UART

1.1Cooperative group

TEAM NUMBER: ______

DUE DATE: ______1st review due date: ______

STUDY TIME:

Study time
(in hours) / Group work / Classroom and laboratory sessions / Sessions out of classroom
Individual / Student 1
Student 2
Student 3

STATEMENT:

My signature below indicates that I have (1) made an equitable contribution to EX 3EX 3 as a member of the group, (2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual member in the completion of this document.

Today’s date: ______

Active members:Roles: (reporter, simulator, etc.)

(1)______

(2)______

(3)______

Acknowledgement of individual(s) who assisted this group in completing this document:

(1)______

(2)______

1.2Abstract

Explain here the most significant developments, results or conclusions about the exercise here. Use the remaining space in on this sheet (200 words maximum).

(This section is mandatory. You must complete it in order to get a mark.)

CONTENT

Designing a UART

1.1Cooperative group

1.2Abstract

1.3Description

1.4Topics

1.5Specifications

1.6Transmitter project (Block II)

1.6.1Specifications

1.6.2Project implementation

1.6.3Phase I: Datapath

1.6.4Phase II: Control Unit (FSM)

1.7Receiver project (Block III)

1.7.1Specifications

1.7.2Project implementation

1.7.3Phase I: Datapath

1.7.4Phase II: Control Unit (FSM)

1.8Final assembling and testing

1.9Project oral presentation

1.10A list of projects of similar complexity

1.11Problem solution (Heading 2)

1.11.1Specifications and theory of operation (Heading 3)

1.12References

1.13Study plan to solve the exercise

1.14Topics and activities checklist

1.15Grading grid

1.16Questions in solving EX2

1.17Improvements of the exercise attending to the review and correction

NOTE:If an activity is labelled as an[Individual task], every student in the group has to do it alone and by his or her own means. The task will aim toinvolve performing simple skills or acquiringe specific content that, which will be used later in cooperative assignments. Your handed inThe solution you hand in must include the particular exercise of each student in the group in a way to demonstrate that everyone has done carried out the jobtask.

NOTE: The proposed assignment and list of activities is mainly anan orientation. Your instructor will clearly explain clearly the sequence of activities or the final planning of the problem to be solved.

NOTE:Blocks The blocks and schematics proposed here are simply orientations of for the final design, which may have slight variations, because it has not been solved before, may have some slight variations. Only a prototype final verification can determine if the project works as expected.

1.3Description

In this third exercise, a project is to be proposed. Cooperative groups will have to plan, develop, simulate, implement and prototype a complex application such as a universal serial asynchronous receiver and transmitter (UART) peripheral. The problem will include multiple blocks and components. HoweverI, in order to standardise the top-down design methodology, and make things easier, the transmitter and receiver units will be conceived as dedicated processors consisting of a datapath (arithmetic components and data registers) and a control unit (the FSM in charge). On the other handT, the baud-rate generator was already designed completely in EX2,as long asalong with many other blocks for the transmitter and receiver units. Thus, this EX3 can thus be seen as considered the final stage in the design of the UART, which which was already initiated in EX1C providing with the provision of the combinational circuits. See the Fig. 1 and read the Chapter III for more details on how a dedicated processor works. In this wayT, thhis project becomes is a compilation of many previously designed components and structures,and givesallowing the student another opportunity to reinforce concepts which that may not be yet be completely understood. A final project assembling and testing can be performed by using a single Altera UP2 or DE0 board looping the serial output (TxD) to the serial input (RxD), or using two boards through a 3-wire cable, transmitting in one boards while receiving in the other in a full duplex communication path.

Fig. 1 The main sections on planning the UART.

In the next Chapter IV, similar projects similar to these dedicated processors, which have already become complex digital systems, will be implemented using microcontrollers instead of FPGA or CPLD. Thus,T we will be able to compare bothhetwo design alternatives will be compared and the figuring out advantages and drawbacks of each approach will be identified.

1.4Topics

The following topics have been listed from based on the course’s specific and cross-curricular learning objectives[1] of the course: #10, #11, #12. After studying Chapter 3 and successfully completing all of the assignments in this task, you will be able to:

------Planning and organising projects ------

1.Follow a top-down strategy to plan the project and a bottom-up sequence to design and test component by component.

2.Assess the utility of project management tools like a Gantt chart.

------The theory ------

3.Explain the concept of a datapath.

4.Explain the concept of "flags" or operation indicators and list the most common flags.

5.Explain the concept of control unit based in on the application of an FSM.

------Particular to this UART project ------

6.Explain how a UART works and list the standard transmissions frequencies used by computers.

7.Explain the wayhow the transmitter unit is organised as a dedicated processor, and design it bottom-up.

8.Deduce a state diagram for the transmitter control unit.

9.Explain how a serial data input line can be correctly sampled in order to recover every bit of information.

10.Deduce a state diagram for the receiver control unit.

11.Explain the wayhow the receiver unit is organised as a dedicated processor and design it bottom-up.

12.Assembly Assemble all the UART modules in a single structural project, test it using ModelSim, synthesise it for a given Altera CPLD or FPGA, and run some tests using laboratory training boards.

------Presentation ------

13.Do an oral presentation of the project consisting of a few slides and upload it at your ePortfolio.

1.5Specifications

A UART subsystem with:

Two2 transmission frequencies: 110 b/s and 9600 b/s.
Use of the Altera UP2 board.
A set of 8 eight switches to input the data to transmit, and a set of 8 eight LEDs to represent the data received.
Pushbuttons to start transmission and other LED’s for indicatingto indicate operation- complete and data- ready.
Datapath + control unit design for the transmitter and receiver subsystems.
Frequency dividers from the board’s 25.175 MHz crystal clock for the baud rate generator. (mModify divider’s coefficients in case ofif using the 50 MHz DE0 crystall clock frequency).

a)Draw some examples on how the UART will operate and determine the functionality of every button and LED to be planned. Write a timing diagram to represent the way in which all the signals will be sequenced to implement the transmission and reception of a byte of information.

(UP2 or DE0 boards: data switches, ST button, ET LED, E_TX button, New Data LED, Error LED, data received LED’s, E_RX button, … Proteus schematic / UP2 / DE0 board showing the main ports)

Fig. 2 Interfacing two systems of a serial interface to demonstrate how it operates. The UP2 board will be used to test the design. The debouncing filter will generate a clean start transmission (ST) pulse.

Fig. 3 Interfacing two systems through a simple 3-wire cable serial asynchronous interface.

Fig. 4 The UART top module consisting of the debouncing filter, the baud rate generator, the transmitter and the receiver (Visio).

b)[Individual task]Explain the functionality of a chip like such as the MAX232 represented in Fig. 5. Determine Find in its datasheet how it is connected as an interface between the transmitter and receiver units on its datasheet. Search for information on the computer’s HyperTerminal application. List its standard transmissions frequencies and determine the wayhow the parity and stop bits can be configured in order to set up a communication.

Fig. 5 Transmitter and receiver sections.

1.6Transmitter project (Block II)

1.6.1Specifications

c)Invent a block diagram and algorithms for the project under way which that consists of dedicateddedicated processor architecture. See Fig. 6 and Unit 3.2. Determine which components will be in the datapath and which one is the control unit. Determine the signals that are going to act as operation indicators or flags (status signals), and which ones will be used to control the datapath sequencing. Apply the Fig. 6 to your machine and draw the architecture of your problem.

Fig. 6 An advanced or complex digital system or a dedicated processor consisting of the combination of a datapath and a control unit (FSM).

Fig. 7 UART transmitter unit envisaged as a dedicated processor (datapath and control unit) for the task of transmitting in series a TX_IN data byte in series using a given protocol.

d)Plan project names, folders, component names, and design flows for every device in the project. The aim is to be able to write the schematic of the project in VHDL language of the project before having it all completing ited. Another important aim is to be able to distribute tasks between the cooperative groups so that all the entire class can work in parallel (concurrently) in on several sections of the same project (as if you were truly professionals in the field).

1.6.2Project implementation

This section is again,also dependent on the specific project under development. Remember that every component has to be verified using functional or gate-level simulations before using it in larger designs. You can also prototype the components using the laboratory training boards.

1.6.3Phase I: Datapath

e)Assemble a project for the transmitter datapath (or operational unit) including all the inner combinational and sequential entities.

Probably,T testing this transmitter datapath alone, is going to likely to be more difficult than assembling the entire transmitter and testing it in order to see whether or not it can send serial through serial_out or not. This is why it is recommended to use the Quartus II RTL viewer simply to check if that everything in the hierarchical design of the datapath is correct.

1.6.4Phase II: Control Unit (FSM)

f)Infer a state diagram for the control unit (transmitter_control_unit) so that it can handle the sequence of operations necessary to transmit data at the specified baud rate and format (110 b/s or 9600 b/s, 1 start bit, 8-bit data, 1 even parity bit, 1 stop bit).

Fig. 8 Inputs and outputs of the transmitter control unit.

Probably,T testing this control unit alone, is likely going to be more difficult than assembling the entire transmitter and testing it in order to see whether or not it can send serial data or not. This is why it is recommended to use the Quartus II state machine viewer simply to check the completeness of the state diagram.

g)Integrate the control unit and the previously designed datapath to the UART transmitter unit entity. Test it through a functional simulation.

1.7Receiver project (Block III)

1.7.1Specifications

h)Invent a block diagram and algorithms for the project under way which that consists of a dedicated processor architecture. See Fig. 6 and Unit 3.2. Determine which components will be in the datapath and which one is the control unit. Determine the signals that are going to act as operation indicators or flags (status signals), and which ones will be used to control the datapath sequencing. Apply the Fig. 6 to your machine and draw the architecture of your problem.

Fig. 9 UART receiver unit envisaged as a dedicated processor (datapath and control unit) for the task of receiving data from a serial input and decoding it as a RX_OUT data byte.

i)Plan project names, folders, component names, and design flows for every device in the project. The aim is to be able to write the schematic of the project in VHDL language of the project before having it all completedcompleting it. Another important aim is to be able to distribute the tasks between the cooperative groups so that all the entire class can work in parallel (concurrently) in on several sections of the same project (as if you were truly professionals in the field).

1.7.2Project implementation

1.7.3Phase I: Datapath

j)Assemble a project for the receiver datapath including all the inner combinational and sequential entities.

Be aware that the counters are slightly different from the ones shown previously in EX1C and EX2. We have to count a delay of 4 clock cycles (counter_mod4) to be centred at half of the start bit, then we have to wait for 8 cycles more in order to sample the incoming bit at about the middle of its length (counter_mod8), and finally, up to 10 samples have to be taken in order to store at in the shift register all the transmissions stream sequence in the shift register (counter_mod10).

Fig. 10 Proposed structure for the receiver counters.

Probably,T testing this receiver datapath alone, is going likely to be more difficult than assembling the entire receiver and testing it in order to see whether or not it can decode serial data or not. This is why it is recommended to use the Quartus II RTL viewer simply to check if that everything in the hierarchical design of the datapath is correct.

1.7.4Phase II: Control Unit (FSM)

k)Infer a state diagram for the control unit unit (receiver_control_unit) so that it can handle the sequence of operations necessary to transmit data at the specified baud rate and format (110 b/s or 9600 b/s, 1 start bit, 8-bit data, 1 even parity bit, 1 stop bit).

Fig. 11 Inputs and outputs of the transmitter control unit.

Probably, testing this control unit alone, is going to be Testing this control unit alone is likely to be more difficult than assembling the entire receiver and testing it in order to see whether or not it can decode serial data or not. This is why it is recommended to use the Quartus II state machine viewer simply to check the completeness of the state diagram.

l)Integrate the control unit and the previously designed datapath to with the UART receiver unit entity. Test it through a functional simulation.

1.8Final assembling and testing

m)Assemble the whole UART system: Debouncing debouncing filter, transmitter (block Block II), receiver (Block III) and baud rate generator (Block I).

n)Circuit synthesis in an FPGA or CPLD, and test the UART interconnecting the serial_out to the serial_in in a UP2 or DE0 boards.

o)Test the UART interconnecting the serial_out from one UP2/DE0 board to the serial_in of another UP2/DE0 board.

1.9Oral presentation of the pProject oral presentation

p)Draw Create a simple 10 10-minuteslong Power Point presentation consisting of a few slides. The idea is to explain orally in group the project (plan, development and results) and the main concepts from this EX3 in a group.

1.10A list of projects of similar complexity

If you like, you can propose us other applications of similar complexity that you may like to designbe interested in designing, such as the following:. Here you are a list below:

-A speed and distance meter for a bike.

-A tachometer or speed meter for a motor.

-A serial transmitter/receiver (an UART peripheral).

-A programmable timer/counter, such as . For example, the Timer0 from the Microchip PIC microcontroller.

-A PWM generator.

-A traffic light controller.

-Real- time clock or chronometer.

1.11Problem solution (Heading 2)

1.11.1Specifications and theory of operation (Heading 3)

This is your text for Heading 4

This is your text ….

Fig. 12 This is your first picture ….

1.12References

[1] . Course wedbpage pagewhere that contains to find a lot of many resources, particularly for the course. Specially, materials from previous editions and the Chapter III.

[2]Hwang, E. O., “Digital logic and microprocessor design with VHDL”, CL-Engineering, 2005. Chapter 11: Dedicated processors.

[3]Problem 3.10. A serial multiplier. A complete design planned as a dedicated processor.

[4]Unit 2.13 from the old former subject Digital Electronics.

[5](Add your own references and modify the previous ones if necessary; there are , because about this subject you can find and study thousands of references on this subject that you can find and studythem).

[6]

1.13Study plan to solve the exercise

Establish a study plan, a task distribution scheme and other requirements to succeed in producing a good solution when working cooperatively: flux diagrams, concept maps, schematics, tables, pictures, etc.

(This section is mandatory. It must be filled in order to get a mark.)

1.14Topics and activities checklist

Topics / Activities / Group member in charge / Comments
1 / 2 / 3

Follow a top-down strategy to plan the project and a bottom-up sequence to design and test component by component.
Assess the utility of project management tools like such as a Gantt chart.

/ (all)

Explain the concept of a datapath.
Explain the concept of "flags" or operation indicators and list the most common flags.
Explain the concept of control unit based in on the application of an FSM.

/ (all)

Explain how a UART works and list the standard transmissions frequencies used by computers.

/ 0, b)

Explain the wayhow the transmitter unit is organised as a dedicated processor, and design it bottom-up.
Deduce a state diagram for the transmitter control unit.

/ c), d), e), f), g)

Explain how a serial data input line can be correctly sampled in order to recover every bit of information.
Deduce a state diagram for the receiver control unit.
Explain the wayhow the receiver unit is organised as a dedicated processor and design it bottom-up.

/ h), i), j), k), l)

Assembley all the UART modules in a single structural project, test it using ModelSim, synthesise it for a given Altera CPLD or FPGA, and run some tests using laboratory training boards.

/ m), n), o)

Do Give an oral presentation of the project consisting of a few slides and upload it at to your ePortfolio.

/ p)

Use this list of topics to think about the subject matter. You may comment on the activities you are dealing with,and say whether they are finished or yet to be studied.

1.15Grading grid

Here you are the wayT the exercise could can be graded as follows.

Part 1
Project specifications and the theory on UART peripheral / Part 2
Designing the transmitter or
the receiver / Part 3
Project assembling and board prototyping. / Part 3
Oral presentation / Total
0, b) / c), d), e), f), g)
or
h), i), j), k), l) / m), n), o) / p)
Scores / 2p / 4p / 2p / 2p
Self-assessment
Instructor’s grades

Explain You could explain here for example which projects or sections you have finished and which are nothave not been done, so that it becomes easy to self-assess your work. Remember that the self-assessment is compulsory; in order to get a mark for the exercise.