Ees801 Seminar Report

EEs801 Seminar report

FinFETs

Venkatnarayan Hariharan

Roll# 04407603

28th Apr 2005

Electrical Engineering Dept.

IIT Bombay

Spring 2005

Change Record

Date / Author / Version / Change Reference /
28-Apr-05 / / 1.0 / No previous document.

Reviewers

Name / Location /
Prof V. Ramgopal Rao / EE Annexe
Prof M.B. Patil / EE Annexe

Distribution

Copy No / Name / Location /
1. / Prof V. Ramgopal Rao / EE Annexe
2. / Prof M.B. Patil / EE Annexe

The copy numbers referenced above should be written into the Copy Number space on the cover of each distributed copy. If the document is not controlled, you can delete this table and the Copy Number label from the cover.

Table of Contents

Acknowledgment 3

Abstract 4

Introduction 5

What is a DG-MOSFET? 5

What is a FinFET? 8

FinFET fabrication 10

Recent work on FinFETs 13

Fabrication efforts 13

Anaytical models 15

Effect of non-vertical fin sidewall 16

Corner effects 16

FinFET circuits, layouts 19

Device width quantization 20

Layout density optimization 20

Conclusions 22

References 23

Acknowledgment

I would like to thank my guide Prof V. Ramgopal Rao for his guidance directly related to this work, as well as for the knowledge I received while attending his concurrently-running lectures in the semester on Nanoelectronics, some of whose topics coincided with the present work.

Abstract

In this report, the basic FinFET structure is described, along with the reasons behind its introduction. The fabrication steps are briefly discussed. Lastly, some recent work on FinFETs is presented, along with the outstanding issues that people have been focusing on.

Introduction

As devices shrink further and further, the problems with conventional (planar) MOSFETs are increasing. Industry is currently at the 90nm node (ie. DRAM half metal pitch, which corresponds to gate lengths of about 70nm). As we go down to the 65nm, 45nm, etc nodes, there seem to be no viable options of continuing forth with the conventional MOSFET. Severe short channel effects (SCE) such as VT rolloff and drain induced barrier lowering (DIBL), increasing leakage currents such as subthreshold S/D leakage, D/B (GIDL), gate direct tunneling leakage, and hot carrier effects that result in device degradation is plaguing the industry (at the device level; there are other BEOL (back-end of the line) problems such as interconnect RC delays which we won’t discuss here). Reducing the power supply Vdd helps reduce power and hot carrier effects, but worsens performance. Performance can be improved back by lowering VT but at the cost of worsening S/D leakage. To reduce DIBL and increase adequate channel control by the gate, the oxide thickness can be reduced, but that increases gate leakage. Solving one problem leads to another. Efforts are on to find a suitable high-k gate dielectric so that a thicker physical oxide can be used to help reduce gate leakage and yet have adequate channel control, but this search has not been successful to the point of being usable. There are problems with band alignment (w.r.t Si) and/or thermal instability problems and/or interface states problems (with Si). The thermal instability problem has led researchers to search for metal gate electrodes instead of polysilicon (because insufficient activation leads to poly depletion effects). But metal gates with suitable work functions haven’t been found to the point of being usable. In the absence of this, polysilicon continues to be used, whose work function demands that VT be set by high channel doping. High channel doping in turn leads to random dopant fluctuations (at small gate lengths) as well as increased impurity scattering and therefore reduced mobility. Indeed, it is felt that instead of planar MOSFETs, a double gate device will be needed at gate lengths below 50nm [1] in order to be able to continue forth on the shrinking path.

What is a DG-MOSFET?

Double gate MOSFETs (DG-FET) is a MOSFET that has two gates to control the channel. Its schematic is shown in Fig. 1.

Fig. 1: Cross section of a generic planar DGFET (from [2])

Its main advantage is that of improved gate-channel control. In conjunction with ultra thin bodies in an SOI implementation (FDSOI DG-FET), it additionally offers reduced SCE, because all of the drain field lines are not able to reach the source. This is because the gate oxide has a lower dielectric constant than Si (assuming the oxide is SiO2), and also because the body is ultra thin. Because of its greater resilience to SCE and greater gate-channel control, the physical gate thickness can be increased (compared to planar MOSFET). Thus it also brings along reduced leakage currents (gate leakage as well as S/D leakage).

There are 2 kinds of DG-FETs:

· Symmetric

· Asymmetric

Symmetric DG-FETs have identical gate electrode materials for the front and back gates (ie. top and bottom gates). When symmetrically driven, the channel is formed at both the surfaces. In an asymmetric DG-FET, the top and bottom gate electrode materials can differ (eg. n+ poly and p+ poly). When symmetrically driven this would end up forming a channel on only one of the surfaces. Both have their advantages and disadvantages. Recent work regarding them will be described in a later section in this report.

Energy band diagrams for symmetrical and asymmetrical DG-FETs are shown in Figures 1 and 2

Fig. 1: Symmetrical DGFET energy band diagram (from [3]) /
Fig. 2: Asymmetrical DGFET energy band diagram (from [3])

The biggest and perhaps the only stumbling block with DG-FETs is its fabrication. One can conceive of 3 ways [4, 7] to fabricate a DG-FET, labeled Types 1, 2 and 3 in Fig. 3.

Fig 3: Three possible realizations of DGFETs (from [7])

Types 1 and 2 suffer most from fabrication problems, viz. it is hard to fabricate both gates of the same size and that too exactly aligned to each other. Also, it is hard to align the source/drain regions exactly to the gate edges. Further, in Type 1 DG-FETs, it is hard to provide a low-resistance, area-efficient contact the bottom gate, since it is buried.

What is a FinFET?

Type 3 DG-FETs are called FinFETs. Even though current conduction is in the plane of the wafer, it is not strictly a planar device. Rather, it is referred to as a quasi-planar device, because its geometry in the vertical direction (viz. the fin height) also affects device behavior. Amongst the DG-FET types, the FinFET is the easiest one to fabricate. Its schematic is shown in Fig. 4.

Fig. 4: FinFET structure, with dimensions marked (from [4])

Because of the vertically thin channel structure, it is referred to as a fin because it resembles a fish’s fin; hence the name FinFET. A gate can also be fabricated at the top of the fin, in which case it is a triple gate FET. Or optionally, the oxide above the fin can be made thick enough so that the gate above the fin is as good as not being present. (This helps in reducing corner effects, discussed later in this report)

It should be noted that while the gate length L of a FinFET is in the same sense as that in a conventional planar FET, the device width W is quite different. W is defined as:

where Hfin and Tfin are the fin height and thickness respectively (see Fig. 4 above. Some literature refers to the fin thickness as the fin width). The reason for this is quite clear when one notices that W as defined above is indeed the width of the gate region that is in touch with (ie. in control of) the channel in the fin (albeit with a dielectric in between). This fact can especially be seen if one unfolds the gate (ie. unwraps it).

The above definition of device width is for a triple gate FinFET. If the gate above the fin is absent/ineffective, then the Tfin term in the above definition is taken out.

On the surface, this freedom in the vertical direction (of increasing Hfin) is a much desired capability since it lets one increase the device width W without increasing the planar layout area! (Increasing W increases the Ion, a desirable feature). However, it will be seen in subsequent sections in this report, that there is a definite range (in relation to Tfin) beyond which Hfin should not be increased, else one encounters SCE [5, 6].

FinFET fabrication

The key challenges in FinFET fabrication are the thin, uniform fin; and also in reducing the source-drain series resistance.

FinFET’s have broadly been reported to have been fabricated in 2 ways [7]:

· Gate-first process: Here the gate stack is patterned/formed first, and then the source and drain regions are formed

· Gate-last process (also called replacement gate process): Here source and drain regions are formed first and then the gate is formed

Fig. 5 illustrates both processes.

Fig. 5: High level FinFET fabrication steps; (a-b): Gate-first process, (c-f): Gate last process (from [7])

FinFET’s are usually fabricated on an SOI substrate. It starts by patterning and etching thin fins on the SOI wafer using a hard mask. The hard mask is retained throughout the process to protect the fin. The fin thickness is typically half or one third the gate length, so it is a very small dimension. It is made by either e-beam lithography or by optical lithography using extensive linewidth trimming [7].

In the gate-first process, fabrication steps after the fin formation are similar to that in a conventional bulk MOSFET process. In the gate-last process, the source/drain is formed immediately after fin patterning. To protect the fin while forming the other regions, doped poly or poly SiGe [7] or even doped amorphous Silicon [8] is deposited on the fin. Then the S/D fan-out pads are patterned, leaving a thin slot between the source and the drain. This distance determines the gate length, which can be further reduced using a dielectric sidewall spacer. Finally the gate oxide is grown and the gate material is deposited and patterned.

To create thin fins very close to each other, the sidewall image transfer (SIT) technique can be used. This technique can help obtain a fin pitch that is half the lithography pitch, which is desirable because:

· It improves device layout density (done by creating very close fins and using a trim level to break the gate continuity, thus separating devices), and

· It enables having the fin pitch smaller than the fin height, which is desirable because it make the FinFET have a greater effective device width than a planar conventional FET.

The SIT technique is illustrated in Fig. 6.

Fig. 6: Sidewall Image Transfer (SIT) technique to create closely spaced, narrow fins (from [7])

Recent work on FinFETs

Fabrication efforts

Ultra thin fins result in better SCE, but increased series resistance. So a fine balance has to be achieved between the two goals. Also, the fabrication process has to be easily integrate-able into conventional CMOS process to the extent possible. Keeping such considerations in mind and others, there have been many efforts to fabricate and characterize FinFETs. Some of them are listed below.

Hisamoto et al reported a gate-last process [8] where they made FinFETs with10nm thick and 50nm tall fins, and 30nm gate length. The fins were patterned using e-beam lithography. The gate material was boron-doped Si0.4Ge0.6, which has the advantage that it is compatible with poly-Si process and its work function is continuously controllable by the mole fraction of Ge. Boron-doped Si0.4Ge0.6 results in a mid-gap work function. The gate was self-aligned to S/D, which was a raised source drain (RSD) structure to reduce series resistance. As was reported, a S/D first, gate-last process can be advantageous when used with a high-k gate dielectric, which mostly have thermal stability issues.

Using a gate-first process, Collaert, et al fabricated FinFETs [9] having (poly, not metal) gate lengths (Lpoly) of 25nm for nFETs and 35nm for pFETs, with 60-80nm tall fins, each being 10nm thick with a 1.6nm gate oxide EOT. The fins were patterned using e-beam lithography. The wafers underwent a H2 anneal to smoothen the fin surface and a 15nm oxidation to round the corners (more on corner effects later in this report). Selective epitaxy to create RSD were not used just to simplify the fabrication process, even though they would have lowered the series resistance.

Kedzierski, et al also fabricated a FinFET using a gate-first process [10] where they made symmetric as well as asymmetric FinFETs. Polysilicon gates were used. The symmetric FinFETs were smaller and had dimensions of Lpoly=60nm (Leff = 30nm), Tfin=10nm and Hfin=65nm. The thin fin was fabricated using optical lithography and a hard mask trimming technique, whose further details are unavailable. The asymmetric FinFETs had p+ and n+ poly gates. They were realizable using gate implant shadowing, because they had a taller 120nm fin. Selective epitaxy was used to create RSD to create devices with low series resistance. Figures 7 and 8 show the Id-Vg curves obtained.

Fig. 7: Id-Vg plot of asymmetric FinFETs (from [10]) /
Fig. 8: Id-Vg plot of symmetric FinFETs (from [10])

More recently, Kedzierski, et al fabricated a high performance FinFET using a gate-first process [11], with a 30nm gate length. Epitaxial RSD, highly angled S/D implants, and CoSi2 silicidation were used to reduce series resistance. High performance nFETs and pFETs with ION of 1460uA/um and 850uA/um were reported. The fin thickness and height was 20nm and 65nm respectively, with a 1.6nm oxide. Many devices were fabricated to specifically study the effect of fin thickness and height on the series resistance. Devices were fabricated in the <100> as well as <110> direction. Fig. 9 shows a cross section.