EE/CPE 428, CPE 528, Homework 1

EE/CPE 428, CPE 528 Homework 1 Solutions

Assigned: January 28, 2003.

Due: February 06, 2003.

Exercise 1. (25)

a. (10) Draw a schematic for the following entity/architecture. Be sure to label all signals.

library IEEE;

use std_logic_1164.all;

entity hw1 is

port(a, b, c: in std_logic;

z: out std_logic;

architecture concurrent of hw1 is

signal w, x, y : std_logic;

begin

w <= not a after 12 ns;

x <= a and b after 12 ns;

y <= c and w after 12 ns;

z <= x or y after 12 ns;

end concurrent;

Solution:

w = NOT(a);

x = AND(a, b);

y = AND(w, c);

z = OR(x, y) = OR(AND(a, b), AND(NOT(a), c))

b. (15) Using the labels, list the order in which the following signal assignments are evaluated if in2 changes from a '0' to a '1'. Assume in1 has been a '1' and in2 has been a '0' for a long time, and then at time t in2 changes from a '0' to a '1'.

entity not_another_prob is

port (in1, in2: in bit;

a: out bit);

end not_another_prob;

architecture oh_behave of not_another_prob is

signal b, c, d, e, f: bit;

begin

L1: d <= not(in1);

L2: c<= not(in2);

L3: f <= (d and in2) ;

L4: e <= (c and in1) ;

L5: a <= not b;

L6: b <= e or f;

end oh_behave;

Solution:

Exercise 2. (30)

a. (5) Under what conditions do the two assignments below result in the same behavior? Different behavior? Draw waveforms to support your answers.

out <= reject 5 ns inertial (not a) after 20 ns;

out <= transport (not a) after 20 ns;

Solution:

When the pulse width of the incoming signal a is greater than 5ns, the statements perform the same. When the pulse width is less than 5ns, the first statement produces no output, while the second one simply delays the short pulse for 20ns.

b. (25) Given the following signal assignments, list all transactions and events (including timings) that expire on the drivers for each signal.

PACKAGE test_utilities IS

TYPE three IS (V1, V2, V3);

CONSTANT bt : TIME := 100 ns;

END test_utilities;

--

USE WORK.test_utilities.ALL;

ENTITY sequential_placement IS END ENTITY;

ARCHITECTURE several_assignments OF sequential_placement IS

SIGNAL a1, a2 : BIT;

SIGNAL z1, z2, z3 : three;

BEGIN

a1 <= NOT a1 AFTER bt;

PROCESS BEGIN

z1 <= V1 AFTER 20 ns;

WAIT FOR 10 ns;

z1 <= V2 AFTER 35 ns;

WAIT FOR 10 ns;

z1 <= V3 AFTER 30 ns;

WAIT FOR 40 ns;

a2 <= NOT a2;

WAIT ON a1;

END PROCESS;

z2 <= V2 AFTER 30 ns, V3 AFTER 50 ns WHEN a1 = '0' ELSE

V1 AFTER 20 ns WHEN a2 = '1';

z3 <= REJECT 40 ns INERTIAL V3 AFTER 30 ns WHEN a1 = '1' OR a2 = '1';

END several_assignments;

Solution:

ns /sequential_placement/a1

delta /sequential_placement/a2

/sequential_placement/z1

/sequential_placement/z2

/sequential_placement/z3

0 +0 0 0 v1 v1 v1

30 +0 0 0 v1 v2 v1

50 +0 0 0 v3 v3 v1

60 +1 0 1 v3 v3 v1

90 +0 0 1 v3 v2 v3

100 +0 1 1 v3 v2 v3

120 +0 1 1 v3 v1 v3

160 +1 1 0 v3 v1 v3

200 +0 0 0 v3 v1 v3

230 +0 0 0 v3 v2 v3

250 +0 0 0 v3 v3 v3

260 +1 0 1 v3 v3 v3

290 +0 0 1 v3 v2 v3

300 +0 1 1 v3 v2 v3

Exercise 3. (25)

a. (10) Given the following declaration:

signal X: bit_vector(3 downto 0) ;

What are the values of the attributes of X listed below?

(i)X'range =

(ii)X'left =

(iii)X'right =

(iv)X'high =

(v)X'low =

Solution:

i) X'range = (3 downto 0)

ii) X'left = 3

iii) X'right = 0

iv) X'high = 3

v) X'low = 0

b. (15) Consider the following type and signal declarations:

type animal is (lion, dog, cat, mouse, horse, fox, cow);

type animal_vector is array (animal range >) of Natural;

signal a1: animal := horse;

signal a2: animal;

signal bv1: animal_vector (fox downto cat) := (1, 10, 2, 6);

For each of the expressions below, indicate whether or not it is a valid expression, i.e. whether or not it could appear on the right-hand side of an assignment to a signal or variable of some type. If it is a valid expression, give its value at time t = 0.

(i)a2

(ii)bv1(mouse)

(iii)mouse < lion

(iv)animal'val(bv1(fox))

(v)animal'pos(cat)

Solution:

(i)valid, lion

(ii)valid, 2

(iii)valid, false

(iv)valid, dog

(v)valid, 2

Exercise 4. (20)

Two architectures for a mux entity are given. Tell if the two architectures are equivalent, i.e. do they give exactly the same behavior? Briefly explain why or why not.

(Assume that i0, i1, and q are defined in the entity declaration as type std_logic.)

Solution:

Consider the simulation using the following test1.do file:

# step through the values

force i0 1 0, 0 50

force i1 0 0, 1 50

force a 0 0, 1 25, 0 40, 1 60

first

ns /mux/i0 /mux/s

delta /mux/i1

/mux/a

/mux/q

0 +0 U U U U U

0 +1 1 0 0 X 0

0 +2 1 0 0 1 0

25 +0 1 0 1 1 0

25 +1 1 0 1 1 1

40 +0 1 0 0 1 1

40 +1 1 0 0 0 0

50 +0 0 1 0 0 0

60 +0 0 1 1 0 0

60 +1 0 1 1 0 1

second:

ns /mux/i0

delta /mux/i1

/mux/a

/mux/q

0 +0 U U U U

0 +1 1 0 0 U

0 +2 1 0 0 1

25 +0 1 0 1 1

25 +1 1 0 1 0

40 +0 1 0 0 0

40 +1 1 0 0 1

50 +0 0 1 0 1

50 +1 0 1 0 0

60 +0 0 1 1 0

60 +1 0 1 1 1

In the architecture first the signal assignment s <= ‘0’; is scheduled for +1 (delta time); the if and case statements are executed based on the “previous” value of signal s.

In the architecture second the variable s is used and the changes in s are visible immediately, so the if and case statements use the changed value for s. So, these two architectures are not equivalent.

CPE/EE 428, CPE 528: HW1Page 1 of 7