ECE6332 Project Review II

Jinrong Yuan

Huihui Wang

Nov. 4th, 2010

  1. Publication Review

Some parts of our project direction have been changed based on Prof. Calhoun’s and TA’s suggestions. The final goal will focus on the influence of strained Si on a 16-bit accumulator rather than a 6T cell SRAM. Based on the literature review of an accumulator with strained Si[1, 2], few paper is about the strained Silicon influence on the accumulator performance no matter multiplex accumulator, phase accumulator or adder accumulator.

For a large range of applications, wide-bandwidth frequency synthesizers are required with attributes of precision frequency control and fast set-on to commanded frequency. Chips composed of a 4-bit adder, a 4-bit register, and lookahead-carry logic capable of connecting up to four chips in a 16-bit parallel adder-accumulator circuit for direct digital synthesis (DDS) have been fabricated by a GaAs foundry for higher speed [1]. This gives us the idea of applying our high-speed s-Si CMOS in the accumulator.

As the fundamental element of an adder/accumulator, the speed of the 1-bit full adder decides the operational speed, power dissipation and the area of the accumulator [3]. To have higher speed accumulator the key is to apply faster full adders, taking the basic components of an accumulator into consideration [4].

  1. Simulation and Design

In order to see the differences in time delay we are going to apply the strained silicon CMOS into the 16-bit accumulator, or to be precise, the adder part, to compare the time delay before/after applying the s-Si. Since the leakage current might be higher due to the low threshold voltage of the s-Si, we might also try to add some modifications to the basic accumulator and the ways to accomplish that can be either adding stack effect in the gates or some other methods which are still in consideration.

So far we have already drawn the schematic of a 16-bit accumulator which is composed of a 16-bit adder, a 16-bit register and a clock signal. Having the 1-bit full adder as the basic component of the adder, the adder and the register are composed of four 4-bit adders and 4-bit registers, respectively.

The following are the simulation results for the stacked/unstacked inverter’s delay and leakage current. (The numbers of the x labels refer to the ratio of the simulated mobility and the original mobility of Si, which is proportional to the strain applied on Si)

We can see clearly from the plots that by adding stack structure (higher VT CMOS) the leakage current can be greatly reduced and the delay of the inverter can be reduced, too.

Fig 3.1 The delay (tpHL)of s_Si inverter without stack /
Fig 3.2 The delay (tPHL)of s_Si inverter with stack

Fig 3.3 The leakage current of s_Si inverter without stack /
Fig 3.4 The leakage current of s_Si inverter with stack
  1. Future Work

Our final goal is to study how the s-Si influence on a 16-bit accumulator performance like delay and leakage current. Towards the final goal, our future work will be done by the following steps:

  1. The study of s-Si influence on the1-bit full adder which influences the delay most in the accumulator. Specifically, it begins with the study of the influence on the delay of AND, OR and XOR gates in the FA adder respectively. Then the optimization of the strained Si distributed among those gates to reduce the delay;
  2. The study of s-Si influence on the register in terms of leakage current;
  3. The optimization of the s-Si in the adder and the register of the accumulator considering the trade off between the delay and leakage current.
  1. Reference

1.Ekroot, C.G.L., S.I., A GaAs 4-bit adder-accumulator circuit for direct digital synthesis. Solid-State Circuits, IEEE Journal of 1998. 23.

2.Niichi Itoh, Y.T., Takeshi Shibagaki, Kouji Nii, Hidehiro Takata, and Hiroshi Makino, A 32X24-bit Multiplier-Accumulator with Advanced Rectangular Styled Wallace-tree Structure. 2005.

3. Shyh-Jye Jou, et al, ‘A Pipelined Multiplier-Accumulator Using a High-Speed, Low –Power Static and Dynamic Full Adder Design’, 1997 IEEE, Vol. 32, No.1.

4.