ECE/CSE 378 Lab 3. Week of January 22, 2007.Rev A

EXPERIMENT: 7-Segment Displays

References

Learning By Example Using VHDL – Advanced Digital Design
Example 11 – 7-Segment Decoder: case Statement
Example 12 – Top-level VHDL Designs
Example 13 – 7-Segment Display: Spartan-3 Board
Example 14 – 4-Bit Binary-to-BCD Converter: case Statement
Example 15 – Binary-to-BCD Converter: for Loops
Spartan-3 Starter Kit Board User Guide: S3BOARD-rm.pdf (available on class website)

LAB

Part 1

1.Do Problem 12.1 on page 54 of the text. Make a new workspace called Lab3 and call the design Part1. Add the file mux7seg.vhd from Listing 12.1. Simulate the program using a hex value of 69 for the switches, sw, and a clock frequency of 50 MHz for btn0. Run the simulation for 100 ns and print out the waveform.

2.Synthesize the design and download the .bit file to the Spartan-3 board. Demonstrate the lab to your lab instructor and obtain his signature for your work on the simulation waveform. Hand in this printout to your lab instructor.

Part 2

1.Make a new design called Part2 in the Lab3 workspace. Write a new VHDL program called sw7seg.vhdthat will implement the top-level design shown in Fig. 1.

The clock divider can be implemented as shown in Listing 1. Complete this program by adding the port map statement for the component x7seg given in Listing 13.3 in the text.

Listing 1

-- Title : sw7seg

-- Design : Part2

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

entity sw7seg is

port(

mclk : in STD_LOGIC;

btn : in STD_LOGIC_VECTOR(3 downto 0);

sw : in STD_LOGIC_VECTOR(7 downto 0);

dp : out STD_LOGIC;

a_to_g : out STD_LOGIC_VECTOR(6 downto 0);

an : out STD_LOGIC_VECTOR(3 downto 0)

);

end sw7seg;

architecture sw7seg of sw7seg is

component x7seg

port(

x : in std_logic_vector(15 downto 0);

cclk : in std_logic;

clr : in std_logic;

a_to_g : out std_logic_vector(6 downto 0);

an : out std_logic_vector(3 downto 0));

end component;

signal q: STD_LOGIC_VECTOR(23 downto 0);

signal clr, cclk: STD_LOGIC;

begin

clr <= btn(3);

dp <= '1';-- decimal point off

-- clock divider

process(mclk, clr)

begin

if clr = '1' then

q <= X"000000";

elsif mclk'event and mclk = '1' then

q <= q + 1;

end if;

end process;

cclk <= q(17);

< add port map statement here >

end sw7seg;

2.Simulate the program using a hex value of 34 for the switches, sw, the formula 1 0 ns, 0 10 ns for the signal clr, and a clock frequency of 50 MHz for cclk. Delete the signals mclk and btn from the waveform view. Add the signals digit and count from the x7seg component to the waveform view. Run the simulation for 200 ns and print out the waveform.

3.Synthesize the design and download the .bit file to the Spartan-3 board. Demonstrate the lab to your lab instructor and obtain his signature for your work on the simulation waveform. Hand in this printout to your lab instructor.

Question: Using the statement

cclk <= q(17);

at what frequency is each digit being refreshed? ______.

if you change the statement to

cclk <= q(18);

what will this new refresh frequency be? ______.

Make this change in your program, implement it again, and download the new .bit file to your board. What do you observe? Why?

Part 3

1.Make a new design called Part3 in the Lab3 workspace. Write a new VHDL program called x7segb.vhd that modifies x7seg.vhd so that leading zeros are displayed as blanks. Write a new VHDL program called sw7segb.vhd that modifies your program sw7segb.vhd from Part 2 to use x7segb.vhd instead of x7seg.vhd.

2.Synthesize the design and download the .bit file to the Spartan-3 board. Demonstrate the lab to your lab instructor and obtain his signature for your work.

Part 4

1.Make a new design called Part4 in the Lab3 workspace. Write a new VHDL program called bcd7seg.vhd that will implement the top-level design shown in Fig. 2. By following the method used in Listings 15.1 and 15.2 in the text write a new VHDL program called binbcd14.vhd that will implement a 14-bit binary-to-BCD converter and add it to the design.

2.Synthesize the design and download the .bit file to the Spartan-3 board. Demonstrate the lab to your lab instructor and obtain his signature for your work.

Question: What hex value of switch settings, sw(7:0), will display the decimal value 9999 on the 7-segment display?

______.

What happens if you enter a larger hex value?