ECE C302n Lab Project # 1

NAME: SECTION:

ECE – C302 Lab Project # 1

Your lab report must contain:

- This top sheet

- Design description including truth table (in all cases) and circuit diagram

(for models in structural style)

- VHDL code

- Simulation results

PART A ( Due week 1)

1. Design , code and simulate a Half Subtractor (in dataflow or behavioral style)

(1)

(The following circuits 2,3,4 must be modeled in structural style)

2. Design , code and simulate a Full Subtractor using two Half Subtractors (2)

PART B (Due week 2)

3. Design , code and simulate a Full Subtractor using basic logic gates (2)

4. Design , code and simulate a 4 X 1 Mux using basic logic gates (2)

Extra Credit ( 1 point)

5. Design , code and simulate a 16 x 1 Mux using five 4 X 1 Muxes (structural style)