Homework #3

ECE 6444 “Silicon-Based Heterostructure Devices and Circuits”

Dr. John D. Cressler

Due Date: Tuesday, 3/11/14 (in my hands by 5:00 pm)

[1]There exists a fundamental device design tradeoff for all bipolar transistors (Si or SiGe or III-V) that forces a reciprocal relationship between the maximum speed (say, peak cutoff frequency), and maximum operating voltage (say, BVCEO). Discuss at length this tradeoff and how it impacts the design of bipolar transistors(for full credit you need at least: 1/2 page of text, using a 12 point Times Roman font, with 1 inch margins, and good English).

[2]Following [1], derive an “upper-bound” for the fT-BVCEO product (the so-called “Johnson limit”) for a Si BJT. How is it possible that this magical speed limit for the IC universe is being routinely exceeded today? You may make reasonable assumptions, but please state them carefully.[1] K. Ng et al., TED, 45, p. 1854, 1998.

[3]Would you expect a SiGe-based field effect transistor (e.g., a SiGe channel MOSFET) or a SiGe-based bipolar transistor (i.e., a SiGe HBT) to be more sensitive to relaxation-induced defect formation? There are several levels of “more sensitive” that one could discuss in this context (e.g., yield, leakage, speed, etc.), so please be concise. You must carefully defend your reasoning(for full credit you need at least: 1/4 page of text, using a 12 point Times Roman font, with 1 inch margins, and good English).

[4]As we will see in Chapter 4, achieving high values of cutoff frequency in a SiGe HBT is most easily accomplished using a triangular-shaped Ge profile. The metallurgical base profile is 30 nm across, and we want to use an ideal triangular profile across this distance.

a) What peak Ge content can we use while maintaining strict thermodynamic stability. You may assume a 20nm Si cap layer on the device. You must show your work, and place your final Ge profile design on a stability diagram.

b) How large is the Ge-induced drift field in the base (in kV/cm)? Assume constant base doping.

c) Do you expect the transport to be dominated by drift or diffusion or both? Please carefully defend your answer.

[5]You have been asked to design a Ge profile which has good immunity to high-injection heterojunction barrier phenomena (we will talk about this formally in Chapter 5, so don’t worry about the physics yet). You are constrained to the profile shape shown below, but are asked to extend the dimension x shown below to its maximum allowable value while still satisfying strict thermodynamic stability. Find x (in nm).You may make reasonable assumptions, but please state them carefully.

[6]From Figure 3.4 (p. 78) for a 50GHz SiGe HBT, determine whether the Ge profile is thermodynamically stable. You must show a stability diagram with the (estimated) Ge profile point on it, as well as how you got your answer. You may make reasonable assumptions, but please state them carefully.

[7]Unlike for Si, a high quality thermal oxide cannot be easily grown on SiGe. Find a reference(s) from the technical literature and discuss at a physical level why this is so. How does one avoid oxidizing SiGe (I am thinking of two things)? Are there alternatives out there? (for full credit you need at least: 1/4 page of text, using a 12 point Times Roman font, with 1 inch margins, and good English).

[8]Your aim is to fabricate the self-aligned SiGe HBT shown in Figure 3.3 (p. 76). You are to outline the individual process steps to build the HBT (do NOT worry about the full BiCMOS – i.e., leave off the FETs), through the first layer of metal. Processing steps may be brief and to the point, and do not require detailed time/temperature/dose conditions. Examples of process steps might include things like:

1) ion-implant boron at high dose / low energy

2) etch by RIE

3) spin on resist and develop pattern for emitter poly definition level (NP)

4) RTA anneal step to activate / drive-in arsenic implant

5) deposit low-temperature oxide (HIPOX)

6) oxidize the poly layer at low temperature

7) etch by RIE to form polysilicon sidewall on mandrel

8) deposit UHV/CVD SiGe epi as i-Si/p-SiGe/i-Si layer

9) perform a chemical mechanical polishing step for planarization

10) deposit undoped polysilicon

...etc.

Consult the literature.You may make reasonable assumptions, but please state them carefully.

[9]For the device you “fabricated” in [8], you need to drawn a top down view of the process mask levels required to fabricate this design (i.e., something like what you would see in Cadence – with all levels in one plot). Create a descriptive “name” for each level, and layout your transistor with reasonable mask-to-mask overlay tolerances. Assume the emitter area to be 0.5x2.5μm2 and make your drawing to scale.State the overall dimensions (in square microns) of your transistor from the outside edge of the deep trench.

[10]You are told that your SiGe HBT design point requires a base Gummel number of 4x1013 cm-2.

a) If your UHV/CVD epi tool can controllably deposit a boron box profile 7.5 nm wide, what should the doping level be in the SiGe growth cycle (in cm-3)?

b) Estimate the base sheet resistance of the final film, if you assume that thermal processing spreads that base width to 17.5 nm after fabrication and the Ge concentration is constant at 10% (in kΩ/square). Make sure you account for Ge-induced mobility changes.

You may make reasonable assumptions, but please state them carefully.

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