ECE 410, Exam 1Spring 2009
ECE 410, Spring 2009 Professor F. Salem
Exam 1 Review
Exam Format:
~10 True/False: covering concepts and theory
~10 Multiple Choice: covering concepts and theory from lecture notes
Matching, fill in the blank, etc. type questions are possible substitutes for the above
~5 Problems: calculation problems that combine concepts learned in homework and class to test your overall understanding of the material.
Honor Pledge
You will be required to sign an honor pledge stating that you did not cheat or witness any cheating. Your exam will not be graded unless the honor pledge is signed!
Calculators
Calculators will probably be allowed at the exam. However, you can not store any information or equations in calculators. Simple function calculators are preferred.
Exam Coverage
All lecture notes and all topics covered in lecture through Chapter 7. All HW1-3 problems. Al Quiz 1-2. Textbook chapters, 2, 3, 5, 6, 7.
List of Topics
• switch-level Boolean logic
• MOSFET voltage characteristics
• switch-level CMOS gates (push-pull networks)
• manipulation and reduction of logic expressions
• construction of CMOS gates from logic expressions
• basic logic functions in CMOS; inverter, NAND, NOR, XOR/XNOR, transmission gate
• resistance and capacitance in CMOS physical layers
• conduction in semiconductor materials (doping, dopants, electron/hole concentrations, etc.)
• physical operation of nMOS and pMOS devices; resistance, capacitance, and current of channel charge
• CMOS physical layers
• physical layout of transistors and basic CMOS gates; use of stick diagrams
• CMOS layout layers and design rule concepts
• CMOS fabrication technologies and process flow
• the layout “cell” concept and cell pitch.
• transistor sizing, scaling, and layout of large transistors
• pn Junction operation, depletion width, built-in potential, and junction capacitance
• the MOSFET capacitor, bias operation regions, determination of surface charge
• MOSFET current flow, regions of operation, physical concepts, and second order effects
• MOSFET RC model, sources and determination of parasitic resistance and capacitance
• Inverter DC transfer characteristics, and transient responses
• NOR and NAND transfer characteristics, and transient responses
• Time Constants, Rise time, fall time, delay, and max frequency of gate operation.
Equations Sheet
The following equations will be provided for you on the exam. Only the following equations and constants will be provided and you will be responsible for knowing what each variable means and when to use each equation.
V = I R / Q = C V; I=dQ/dt=C(dV/dt)n p = ni2 / = q(nn + pp)
R = L/A / Jx = Ex
Cox = ox/tox / Qc = -CG(VG-Vtn)
n = nCox (W/L) / Rn = 1 / n [(VDD-Vtn)]
CSB = Cj ASbot + Cjsw PSsw
CDB = Cj ADbot + Cjsw PDsw / CGS = ½ CG
CGD = ½ CG
region / nMOS equations / pMOS equations
Cutoff / /
Triode / /
Saturation
(Active) / /
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ECE 410, Exam 1Spring 2009
Constants
kT = 0.026 eV, at room temperature
k = 8.62x10-5 eV/K, Boltzman’s constant
VT = 0.026 V, thermal voltage
q=1.6x10-19 C (coulombs)
ni = 1.45x1010cm-3, Si at room temperature
0 = 8.85x10-14 F/cm
OX = (3.9) 8.85x10-14 F/cm
si = (11.8) 8.85x10-14 F/cm
Quadratic Equation:
ax2 + bx + c = 0
DeMorgan’s Rules
(a * b)’ = a’ + b’
(a + b)’ = a’ * b’
Useful Logic Properties
1 + x = 10 + x = x
1 * x = x0 * x = 0
x + x’ = 1x * x’ = 0
a * a = aa + a = a
ab + ac = a (b+c)
properties which can be proven
(a+b)(a+c) = a+bca + a'b = a + b
a + ab +ac = a
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