9/12/04
Lab 1 – Basic Gates
Xilinx ISE ABEL Tutorial
1.Double click the Xilinx ISE Project Navigator icon on the Desktop to start the Project Navigator, then maximize the window.
2.On the Project Navigator toolbar, click: File => New Project… .
3.In the New Project window, first click the browse button and browse for the cse171 folder. If the cse171 folder does not exist, browse for the (C:) drive, click OK, then type cse171 in the Project Location text box.
4.Add a back slash (\) and your last name as the folder name in the Project Location.
Then, select HDL as the Top-Level Module Type.
5.Finally, type Gates as the project name and click Next. . (Notice that Gates is automatically added to the Project Location.)
6.Select the following property values in the New Project window. Then click Next.
7.In the New Project window, click: New Source... .
8.Select ABEL-HDL Module and type Gates in the File Name: box. Select Add to project and click Next.
9.In the Define ABEL-HDL Source window, type in this list of pin names. Click Next.
10.Click Finish.
11.Click Next.
12.(Functional blocks may be added to a design using this window.) Click Next.
13.Click Finish.
14.This skeleton source will be created.
15.Modify the source code by adding a title line with your names and date, declarations with comments, pin numbers and the output types.
16.Complete the source code by adding these equations and test vectors.
Save this file.
17.Simulate the program by selecting Gates-vectors and double-clicking Generate BLIF Simulation Report.
18.Double-click View BLIF Simulation Report under BLIF Simulation Report.
If there are no errors, print out the BLIF Simulation Report.
19.Select Gates (Gates.abl) and double-click the Generate Programming File process.
20. If there are no errors, click the edit window Gates.abl tab and print out a copy of this file.
21.Prepare the PLDT-3 board by connecting jumper wires between connector T2 and pin 72 of header HD2 and between T4 and pin 71 of HD2. Connect the PC printer port cable to jack J2 of the PLDT-3 board, connect the 9V DC power module to jack J1 and plug the power module into AC power. Turn all toggle switches on switch blocks S6 and S7 to Off (down). Double-click Configure Device (iMPACT) under the Generate Programming File process.
22.Select Boundary-Scan Mode and click Next.
23.Select Automatically connect to cable ... and click Finish.
24.Click OK.
25.Double-click your Gates.jed file entry.
26.Right-click on the image of the Xilinx chip and select Program…
27.Make sure Erase Before Programming and Verify are both checked, then click OK.
28.Following successful programming, the Programming Succeeded message is displayed.
The PLDT-3 Programmable Logic Device Trainer Board is now programmed and ready for testing.
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