ECE 477 Digital Systems Senior Design Project 8/09
Homework 5: Theory of Operation and Hardware Design Narrative
Team Code Name: Digital Sound Projection (DSP) Group No. 6
Team Member Completing This Homework: Shao-Fu Shih
E-mail Address of Team Member:
Evaluation:
SCORE
/DESCRIPTION
10 /Excellent – among the best papers submitted for this assignment. Very few corrections needed for version submitted in Final Report.
9 /Very good – all requirements aptly met. Minor additions/corrections needed for version submitted in Final Report.
8 /Good – all requirements considered and addressed. Several noteworthy additions/corrections needed for version submitted in Final Report.
7 /Average – all requirements basically met, but some revisions in content should be made for the version submitted in the Final Report.
6 /Marginal – all requirements met at a nominal level. Significant revisions in content should be made for the version submitted in the Final Report.
* /Below the passing threshold – major revisions required to meet report requirements at a nominal level. Revise and resubmit.
* Resubmissions are due within one week of the date of return, and will be awarded a score of “6” provided all report requirements have been met at a nominal level.
Comments:
1.0 Introduction
Digital Sound Projection consists of a transmitter and a receiver base station for transmitting digital audio through the air. Since the transmitter is battery based, there will be a trade off between SNR and power consumption. The receiver station was designed to either receive the digital audio or to accept analog input from Analog to Digital Converter (ADC). The base station then will perform an N point Fast Fourier Transformation (FFT) to get a rough estimation of frequency domain. By adjusting the frequency bands, users will be able to apply EQ effects by interacting with a user interface. After all the computations are done, the Digital Signal Processor (DSP) then will be send to Digital to Analog Converter (DAC) for reconstructions. On the PCB, left and right channels are laid out separately to reduce the effect of inter-channel contamination. The digital circuitry is also separated from analog components to reduce Electromagnetic Interference (EMI) effects.
2.0 Theory of Operation
The transmitter contains three major subsections which includes microphone input section, unit control section, and wireless transmitter section. The microphone input section uses Texas Instrument’s (TI) PGA2505; a digital SPI control with gain up to a thousand microphone preamp accepts small signal differential input. PGA2505’s output is set to be 0-5V for Vout+ and Vout- with Vcom = 2V in order to work with PCM4222’s (ADC) Vref value. To further process the input, the signal is passed to PCM4222 which quantizes our analog input into I2S output with 48kHz/24bit bit rate.
The Nordic’s semiconductor nRF24Z1 wireless transceiver then receives I2S input from PCM4222 and performs bit truncation to compress the input down to 16bits. nRF24Z1 also provides channel coding to guarantee its signal quality between transmitter and receiver; it generates protection codes and CRC checksum to prevent wireless interference. To modulate the digital audio for transmission, nRF24Z1 passes data to a Gaussian filter and then multiplies its output with 38 different carrier frequencies between 2.4GHz to 2.45GHz simultaneously to select an optimal operating frequency. In order to transmit at 2.4GHz, a high frequency capacitor is used between antenna ground and digital ground to prevent interference.
All the devices above are controlled by an ATmega168 microcontroller, which also runs the UI on the transmitter side. The clock speed of ATmega168 is at 4MHz, which is sufficient to operate our UI and control our nRF24Z1. To make sure the device runs on a same frame for I2S data, a crystal clock of 12.288MHz is used to synchronize between PCM4222 and nRF24Z1.
On the transmitter, all the analog output is driven between +4.5V and -4.5V and all the digital components operate at 3.3V. All the above voltage is generated by TL497, a step-up, step-down, and inverting switching voltage regulator which converts 3-cell battery pack 4.5V into desired voltages.
On the receiver, inputs come from either nRF24Z1 or line-in from 3.5mm headphone jack. nRF24Z1 receives digital audio from an antenna; the chip then utilizes a Phase Lock Loop (PLL) with self-clock regeneration to decode Gaussian Phase Shift Keying (GPSK) back to I2S with additional checksum and error corrections. From 3.5mm line-in port, a PCM4222 is used to quantize 1V<Vpp<4V analog signal to I2S digital audio signal. Since mic-in is not implemented, PGA2505 is not necessary on receiver side.
I2S signal from either transmitter or line-in is then sent to Analog Devices’ SHARC ADSP-21262 for EQ and digital mute processes. SHARC takes I2S input and saves the sample points into two separate N (N = 1024 or 2048) real number floating point buffers with fill time of 1/48000 * N = 20 or 40ms for left and right channels. Since user will be able to adjust input signal’s behavior in frequency domain, Short Time Fourier Transformation (STFT) is needed to convert time domain into frequency domain. An optimized FFT function provided by the Virtual DSP library from Analog Device is used. In order to FFT to each individual channel, one complex N point and one real N point buffer is allocated; N twiddle coefficients (complex points) are generated and saved into memory. After FFT calculation and frequency convolutions (EQ effects and other frequency based operations), inverse FFT (IFFT) of length N is used to convert the frequency domain back to time domain in order to reconstruct the digitized signal. The entire computation should not exceed the time required to build N samples input buffers based on 200MHz clock frequency of the SHARC, which is insignificant compared 20ms to 40ms required sampling time.
PCM1792A reconstructs the processed digital audio sent from SHARC to analog current driven differential outputs, Iout+ and Iout-. A set of bi-amp I/V current integrators are implemented to convert Iout to Vout with Vavg = 2V and Vpp = 4V. To generate both 1/4” headphone output and RCA output, the signal is then spits into two. RCA is generated by using another bi-amp configuration to combine differential input into singled output, and a 1/4” headphone jack is driven by TI’s TPA6120.
TPA6120 takes differential inputs for both left and right channels and combine them to single output with +15Vcc+ and -15Vcc- which then drives the 1/4” headphone jack for both left and right channels in order to drive external headphones. TPA6120 also provides an ultra-low THD and high SNR for its power rating and is generally used to drive high impedance 1/4” headphones.
The receiver uses a 9V, 500mA wall wart and four TL497 voltage regulators. The output voltages are +15V and -15V for op-amps, +5 for Vcc on PCM1792 and PCM4222, and +3.3 for Vdd on our digital devices. The SHARC requires 1.2V supply for its internal core voltage which will be generated from +3.3V with voltage divider.
3.0 Hardware Design Narrative
On the transmitter, three pins on ATmega168 microcontroller will be utilized for SPI: serial clock, master out slave in, and slave devices master in slave out, with additional two pins to select between PGA2505 and nRF24Z1. To give user control of output volume on the receiver from transmitter, two pins are used for reading from push buttons. Also there will be two additional pins on ATmega168 to read the user input regarding and analog input gain selection. On ATmega168, all the unused pins are tied to ground to avoid EMI effects.
PGA2505 communicates with ATmega168 using SPI to adjust gain between 0dB to 60dB. In order to generate 0-5V differential output for PCM4222, PGA2505 reads Vref from PCM4222, uses it as an output common ground (Vcom), and generates voltage outputs accordingly.
PCM4222 is set to PCM mode with 12.288MHz clock signal coming from nRF24Z1. After PCM4222 digitizes the analog input, it is then sends the digital audio to nRF24Z1. I2S with word length of 24bits is selected for this operation, it uses three pins for I2S data, I2S bit clock, and I2S framesync. On PCM4222, all the unused modes including DSD and multi-bit modulator mode are disabled.
nRF24Z1 is configured by ATmega168 with one mode select (either Tx or Rx) pin, two volume control inputs de-bounced by ATmega168, and the SPI bus. nRF24Z1 reads I2S input from PCM4222 and adds additional volume reading to the end of the audio bit stream then transmit it into air using a 2.4GHz antenna. On nRF24Z1, antenna 2 output is tied to ground and all the unused pins are tied to ground to prevent EMI effects.
On the receiver, PCM4222 is set to have the same data output format as the one on the transmitter. Chip select pins are implemented to digital audio source between nRF24Z1 and PCM4222. All the unused I/O are tied to ground and all the unused functions are disabled for both nRF24Z1 and PCM4222.
SHARC Digital Signal Processor receives I2S signal from either PCM4222 or nRF24Z1 and buffers the input data stream in internal RAM to perform Digital Signal Processing on digital audio. Since SHARC has the most of GPIO pins and fastest clock speed, it is used as master SPI device to select between different SPI controlled subsystems and sends out reset flag to each subsystem every time the receiver restarts. Also, SHARC requires an additional SPI based flash chip to store the programs.
An ATmega168 microcontroller is also implemented to show user device status, to read user inputs, and to drive the LCD display. The microcontroller is driven by SHARC over SPI buses and reads user input from push buttons and rotary knobs. Analog Rotary knobs and push buttons will take eight pins on the microcontrollers while LCD display is driven by two serial ports, two for LCD read/write, and one for LCD chip select.
4.0 Summary
The transceiver is designed with low power consumption. Minimum amount of chips are used to reduce power consumption and pins connections. The transmitter uses ATmega168 as a central processing unit to controls PGA2505, PCM4222, and nRF24Z1. PGA2505 is connected to singled input to differential output converter and generates high gain voltage output. PCM4222 reads the voltage readings from both + and – of the differential input and outputs I2S digital audio to nRF24Z1. nRF24Z1 accepts I2S signal and performs input compression and channel coding then sends the modulated signal into air with 2.4GHz an external antenna.
On the receiver, nRF24Z1 receives input signal from an external antenna and decodes the modulated input to I2S digital audio. An additional PCM4222 is used on the receiver to read analog input on the receiver and converts it to I2S digital audio as well. SHARC DSP has chip select to select input source between nRF24Z1, PCM4222. SHARC performs frequency analysis and apply frequency convolutions to digital audio. After frequency operations, SHARC then sends the processed digital audio to PCM1792. PCM1792 takes the I2S data and converts it back to current driven differential outputs. ATmega168 is used on the receiver as well in order to show device status, to read user inputs, and to drive LCD display. ATmega168 reads user inputs from a rotary encoder and three push buttons. All the subsystems on the receiver side besides PCM4222 are controlled by SHARC using SPI buses, and the entire system is powered by a 9V DC input with linear voltage regulators.
List of References
[1] Analog Devices Inc., ADSP-21261/21262/21266 Processor Datasheet, Jul. 2009. [Online]. Available: http://www.analog.com/static/imported-files/data_sheets/ADSP-21261_21262_21266.pdf
[2] Texas Instruments Inc., PCM4222 Analog-to-Digital Converter Datasheet, Mar. 2007. [Online]. Available: http://www.ti.com/lit/gpn/pcm4222
[3] Texas Instruments Inc., PCM1792A Digital-to-Analog Converter Datasheet, Nov. 2006. [Online]. Available: http://www.ti.com/lit/gpn/pcm1792a
[4] Texas Instruments Inc., PGA2505 Digital Controlled Microphone Preamplifier Datasheet, Jun. 2009. [Online]. Available: http://www.ti.com/lit/gpn/pga2505
[5] Texas Instruments Inc., TPA6120A2 High Fidelity Headphone Driver Datasheet, Mar. 2004. [Online]. Available: http://www.ti.com/lit/gpn/tpa6120a2
[6] Texas Instruments Inc., TL497 Switching Voltage Regulator Datasheet, Feb. 2005. [Online]. Available: http://www.ti.com/lit/gpn/tl497a
[7] Nordic Semiconductor, nRF24Z1 2.4GHz Wireless Audio Streamer Datasheet, Jun. 2006. [Online]. Available: http://www.nordicsemi.com/index_popup.cfm?obj=misc&act=download&pro=86&prop=607
[8] AVR ATmega168, 8-bit Microcontroller Datasheet, Jul. 2009. [Online]. Available: http://www.atmel.com/dyn/resources/prod_documents/doc2545.pdf
Appendix A: System Block Diagram
Figure 1: Updated Transmitter Block Diagram
Figure 2: Updated Receiver Block Diagram
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