Technology behind Crusoe Processors
Word Count: 602
Crusoe processors come as a refreshing change to the Intel dominated chip market with their Pentium like designs based on pipelining and Tomasulo architectures. The idea behind Crusoe is very interesting and rightly as the author claims may offer a fight in the future to Intel’s unquestionable superiority in today’s market. But this does not mean it has the capability to do so now (date on paper, Jan 2000). It has certain gray areas which have been either deliberately left out or conveniently forgotten by the authors of the paper.
The kernel idea of the design is using software for all code optimization and hardware only for executing the code. This at a glance, we would understand, would offer some far-reaching advantages in optimizing code, which can be leveraged to run on a processor for a lesser time for the same output. This software they call the ‘Code Morphing Software’. It stands between the Operating system, the applications etc and the processor as a middle man taking high level x86 code and converting it into VLIW (Very LargeScale Instruction word) instruction format. It then optimizes the code using its advantage of infinite ‘window’ and suave optimization algorithms to streamline the code and feed it to the processor waiting to run the simplified code in a serial manner in an uninterrupted fashion.
The one obvious advantage they have derived has been the low power consumption resulting from the simplification of the hardware design making it an attractive buy for mobile and low powered devices. This however may not be the ultimate goal of the chip architects. It is evident that they want to challenge the competitor by adopting a different approach to chip design and hopefully come out with something astounding in the next few years and surprise the market. This may only be an intermediate by product of that exercise. The authors claim that they are able to tackle redundant data better than the market leaders and their performance on such applications such as multimedia vindicates their stand. Towards the end of the paper they also describe some of their techniques they have employed to achieve that end which are quite appealing.
However in their own words the Crusoe fails to stand up to standard benchmarks due to the lack in data redundancy in them. However they have not mentioned an empirical observation in comparison to the latest Intel chips which could have proved their argument convincingly. However their unwillingness to do the same may suggest that their performance is not yet tantamount to Pentiums even on similar applications. Their argument is centered around the heat sink and the merits of owning a low powered processor. One also intuitively tends to think that the additional load of running the ‘Code Morphing software’ on the processor may take away any gains from the code optimization front. The author does mention that point, but brushes it away as a small issue. Comparing the Crusoe approach with the other more studied approaches in class like Tomasulo shows the researchers willingness to take the less trodden path which deserves ample appreciation.
The processor seems to be an ideal substitute to Pentium varieties for Mobile computing, but the sheer market presence of Intel must be a huge impendence in making headway. I would opine that the idea behind the architecture is not intended for simply specialized applications but truly provide an alternate path towards chip design. In that perspective the architecture is a success, may be not as much commercially but certainly in lighting up new ideas in the minds of fellow researchers.