IITC/AMC 2014 Tip Sheet

IITC/AMC 2014 Tip Sheet

Page 2

May 20-23, 2014 w Doubletree Hotel w San Jose, CA

http://www.ieee.org/conference/iitc

Editor Contacts:

Dr. Vincent McGahay

Program Co-Chair, 2014 IITC/AMC

Dr. Deepak Chandra Sekar

General Co-Chair, 2014 IITC/AMC

Dr. Tokei Zsolt

General Co-Chair, 2014 IITC/AMC

For Immediate Release

Tip Sheet for the 2014 IEEE Joint Conference of the

International Interconnect Technology Conference (IITC)

and the Advanced Metallization Conference (AMC)

The 17th annualIITC will be held May 21 – 23, 2014 in conjunction with the 31st AMC at the Doubletree Hotel in San Jose, California. It will be preceded by a day-long workshop on “Manufacturing of Interconnect Technologies: Where are we now and where do we go from here?” on Tuesday, May 20.This tip sheet will provide an advance look at the conference and workshop programs. Further details are available at the conference website: http://www.ieee.org/conference/iitc Please contact us for interviews with conference organizers, for images or for further information.

NOTE: See pages 5-7 for:

·  Why interconnect technology is critical to electronics

·  Definitions of technical terms

The 2014 IITC/AMC will feature a keynote speech from Dr. Randhir Thakur, Executive Vice President and General Manager of the Silicon Systems Group of Applied Materials. Following this, there will be multiple sessions on 2D and 3D interconnect materials, processes, reliability and systems. Some of the highlights of the technical sessions are:

Near-Zero Keep-Out Zone for Through Silicon Via Technology

Through Silicon Vias (TSVs), an important component of 3D chip stacking technology, typically have a “keep-out zone” around them, where transistors are not placed. This is due to co-efficient of thermal expansion mismatch between the copper TSVs and silicon, which introduces tensile stresses in the silicon and changes transistor performance. These keep-out zones are typically >7mm, which adds constraints for design and leads to die size penalties.

Copper shrinkage results in tensile stress in the silicon while CMP stop layer shrinkage results in compressive stress in the silicon

In this work from GLOBALFOUNDRIES, a CMP stop layer is specially designed such that it introduces compressive stresses on the silicon and compensates for the tensile stresses introduced due to copper TSVs. The result is a near-zero keep-out zone for TSV technology, that is validated with simulations as well as experiments.

[5.2. M. Rabie, et al., “Novel Stress Free Keep Out Zone Process Development for Via Middle TSV in 20nm CMOS”, GLOBALFOUNDRIES]

Experimental Demonstration of Monolithic 3D-IC Technology

Monolithic 3D-ICs

Sizes of today’s TSVs are in the 5um range. Monolithic 3D technologies offer TSVs in the 50nm range, which allows dense connectivity between different layers in a 3D-IC. In this paper from CEA-LETI, such dense connectivity is shown to provide 55% area reduction and 47% energy-delay product improvement for a 14nm FPGA design. Transistor technologies that allow monolithic 3D integration are experimentally demonstrated.

[12.1. P. Batude, et al., “3D Sequential Integration Opportunities and Technology Optimization”, CEA-LETI (Invited)]

Graphene Experimentally demonstrated to have Lower Resistivity than Copper

Theoretical studies indicate graphene could offer lower resistivity than copper. However, experimental evidence of the improved resistivity has been elusive. This paper from AIST demonstrates 8nm wide 6.4nm thick graphene interconnects with a resistivity of 3.2uohm-cm, which is significantly better than copper with similar dimensions. This milestone for graphene interconnect research is expected to motivate the process integration research that is required to take the technology to the next level.

[4.5. D. Kondo, et al., “Sub 10nm wide intercalated multi-layer graphene interconnects with low resistivity”, AIST]

8nm wide graphene interconnects

Mean Free Path for Vertical Carbon Nanotube Interconnects approaches Copper

Carbon Nanotube (CNT) vias in integrated structures

Carbon nanotubes (CNTs) have been explored as a material for vertical interconnects since they can handle higher current densities than copper and offer ballistic transport. This paper from IMEC demonstrates a 5x improvement in electron mean free path for CNTs compared to previous work. The CNT mean free path of 24-74nm approaches copper. Contact resistance is improved significantly compared to previous work as well.

[4.3. M. van der Veen, et al., “Electron Mean Free Path for CNT in Vertical Interconnects Approaches Copper”, imec]

Process Integration of 3D Capacitors into 22nm Interconnect Stacks

3D capacitors embedded into the BEOL

Embedded DRAM is becoming important for high-performance ICs. This necessitates integrating sophisticated 3D capacitor structures into the interconnect stack. This paper from Intel shows a process integration flow for a 3D capacitor that provides excellent yield and retention times greater than 100us at 95oC. The 3D capacitor advances allow an industry-leading 17.5Mb/mm2 memory array density.

[8.1. R. Brain, et al., “Integration of a 3D Capacitor into a Logic Interconnect Stack for High Performance Embedded DRAM SoC Technology”, Intel (Invited)]

Cobalt and Silicon Nitride Barrier Cap Films for Copper Low k Interconnects

10x improvement in electromigration lifetimes with multi-layer SiN and selective cobalt cap layers. 1000x improvement in electromigration lifetimes with multi-layer SiN cap, cobalt cap and wrap-around cobalt liners.

Scaling causes challenges with interconnect reliability. Both time-dependent-dielectric-breakdown (TDDB) and electromigration lifetimes for interconnects drop rapidly. In this paper, a multi-layer SiN cap process is developed that shows higher breakdown and lower leakage compared to conventional SiCNH caps. Selective cobalt caps in combination with the multi-layer SiN cap are shown to provide a 10x improvement in electromigration lifetimes. Wrap-around cobalt liners in combination with the cap layer schemes are shown to provide a 1000x improvement in electromigration lifetimes.

[4.4. D. Priyadarshini, et al., “Advanced Metal and Dielectric Barrier Cap Films for Cu Low k Interconnects”, IBM, Applied Materials]

In addition to these, IITC/AMC 2014 features several excellent invited and contributed papers. Please see the advance program for more details: http://www.iitc-conference.org/program.html

To allow conference attendees to discuss and learn about the latest interconnect manufacturing developments, a 1 day workshop is scheduled before the conference starts. This workshop, which is available free-of-charge to conference attendees, is titled “Manufacturing of Interconnect Technologies: Where are we now and where do we go from here?” It features manufacturing experts from major industry players who will present their views on the subject. A panel discussion at the end of the day will allow open discussion on manufacturing topics and audience participation. The workshop program is available to view at: http://www.iitc-conference.org/workshop.html

Visit the 2014 IITC/AMC to keep abreast of these exciting developments! If there are any questions or requests for more information, please contact Deepak Sekar () or Vincent McGahay () or Tokei Zsolt ().

What is interconnect and why is it so important?

“Interconnect” is the wiring system that connects transistors and other components on an integrated circuit, or computer chip. It may also refer to chip-to-package or chip-to-chip interconnections. Transistor speed used to be the limiting factor for chip performance, but with today’s multi-million-transistor chips, the interconnect itself has become a limiting factor. This is because the electrical resistance of the wires, or lines, increases as they are made thinner to accommodate more transistors. It also arises because capacitive coupling can occur among adjacent lines spaced very closely together. Both inhibit the passage of signals.

The interconnect problem threatens to retard the development of chip technology, which in turn threatens the progress of the electronics industry, one of the world’s largest. IITC/AMC papers address this problem directly.

Copper lines offer less resistance and higher current-carrying capability than the previously used aluminum lines, but at small geometries surface scattering effects increase the effective resistivity, which has led to interest in alternative conductors such as graphene and carbon nanotubes. Standard silicon dioxide insulator (or dielectric) around the lines creates a high parasitic capacitance at narrow spacings with concomitant signal delays and increased power consumption. This had led to the introduction of and continued search for substitute materials. A dielectric’s relative permittivity is expressed as “k.” The lower the k, the faster the signal propagation speed and the lower the power consumption. (Vacuum, the perfect low permittivity material, has k=1; silicon dioxide has k~4.) The challenge with dielectric materials with very low k-values is that they are porous and generally more fragile than oxide dielectrics. Carbon-doped oxide (or SiCOH) low k dielectrics can be easily damaged by typical chip-making processes such as exposure to harsh plasma during photoresist-stripping and to chemical-mechanical polishing, used to planarize each interconnect layer.

The semiconductor industry introduced the first carbon-doped low k dielectrics with k~3 in the 90nm technology node. The 45/40nm nodes saw introduction of enhanced SiCOH low k (k~2.7) and early porous ultra low k (ULK, k~2.4). The 32/28nm nodes developed mechanically robust ULK films (k~2.5) which are becoming pervasive in the 22nm technology entering early production. Focus in the 20nm and 14nm nodes has been on patterning challenges but research and development on dielectrics with enhanced mechanical properties and extreme low k (k~2) remains active. Additionally, at the advanced technology nodes’ smaller dimensions, there is an increased focus on new materials and processes to improve the reliability and manufacturability of copper based interconnects. These include barrier, seed, copper filling, and capping technologies.

3D Interconnects

The electronics industry continually strives to place more functions in the same size or smaller packages. One way to do that is with 3D integrated circuits, where individual chips are thinned (usually), stacked and then interconnected so they function as a single unit. These stacks are challenging to fabricate, and despite much progress in recent years the industry is still trying to determine the best ways to accomplish 3D interconnect architecture.

There are a variety of 3D techniques under consideration, but many of them require the etching and filling of relatively large, deep holes through the backside of the wafer, called through-silicon-vias, or TSVs. Processes such as deep etching, highly conformal insulator deposition, and high-aspect-ratio metal fill are needed to create these TSV structures. The demand for these types of applications warrants special consideration in interconnect technology, and IITC has included this discussion in its technical sessions.

Here are definitions of some technical terms used throughout this Tip Sheet:

·  CMOS -- Most transistors today are FETs, or field-effect transistors. Most FETs are built with CMOS manufacturing technology (complementary metal oxide semiconductor).

·  CMP (chemical-mechanical planarization) -- The process of planarizing, or making flat, the surface of an in-process wafer in preparation for the next manufacturing step.

·  Electromigration -- A huge reliability problem. At tiny dimensions, copper tends to physically move with current flowing through it, leading to gaps or outright breaks in copper interconnect

·  Front-End/FEOL & Back-End/BEOL -- Transistors and other active devices are built first on chips at the so-called “front end of the (manufacturing) line” (FEOL), and the interconnect is built later on, at the “back end” of the (manufacturing) line (BEOL).

·  Integrated Circuit -- A tiny electrical circuit built on a semiconducting substrate.

·  Low-k/Interconnect -- Interconnect refers to the copper lines that connect devices on a chip. The tiny widths and close proximity of adjacent lines introduce resistance and capacitance delays that can hinder chip performance. A low-k dielectric is needed to insulate the copper lines, but these materials are fragile and pose many challenges. The lower the “k” value, the better the insulating properties.

·  Scaling/Integration -- Scaling is making circuitry such as transistors smaller so that more will fit on a chip. Integration is combining more circuit elements on a chip to add more functions at less cost.

·  Technology Generations/Nodes -- Each new generation of chip technology (or “node”) is designated by half the distance (e.g. half the pitch) between the closest adjacent printed lines it can produce. This is measured in nanometers (nm). Most major semiconductor companies have introduced 90-nm chips and some have 65-nm chips in volume production. The next generation, 45nm, has recently begun to enter the marketplace.

·  How Interconnect Is Built--

1.  Horizontal trenches are etched into a thin film of insulating material on a silicon substrate. Vertical holes called vias are patterned and etched as well. The vias electrically connect copper lines in different layers. The order of trench and via patterning depends on the manufacturing scheme used.

2.  The entire wafer, including the bottoms and sides of the trenches and vias, is coated with a liner/barrier material and copper. Excess material is removed via chemical-mechanical polishing (CMP), leaving the surface flat.

3.  To finish a layer, an insulating capping material is deposited on top of the copper lines. This surface then becomes the foundation for the next layer, built in the same fashion.

4.  Advanced chips can contain over 15 layers of copper lines, extending across the chip in myriad pathways. Some lines carry electrical signals, others conduct power.