Experiment 4 Arithmetic Processor
1Objective
To study the algorithmic state machine (ASM) chart, some register transfer operations, and the design of state generator and control circuit.
2Problem description
The design is an arithmetic processor which can perform four of the following arithmetic instructions with two selection signals Op2 Op1.
InstructionFunction
A A + BAddition
A A - BSubtraction
A A + 1Increment A
A A - 1Decrement A
A B + 1Increment B
A B - 1Decrement B
A -ANegate A
A -BNegate B
Ten sets of four arithmetic functions and their corresponding operation code Op2 Op1 are listed in Table 1. The function set assigned to you can be found on p.11.
Table 1 Arithmetic function sets.
Op2 Op1 / Arithmetic function set1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10
00
01
10
11 / A-B
A+B
A+1
B-1 / A-B
A+B
A-1
B-1 / A-B
A+B
A-1
B+1 / A-B
A+B
-A
B-1 / A-B
A+B
A-1
-B / A+B
B-A
A+1
B-1 / A+B B-A
A-1
B-1 / A+B B-A
A-1
B+1 / A+B
B-A
-A
B-1 / A+B B-A
A-1
-B
As shown in Figure 1, two universal shift registers R1 and R2 (IC type 74194) are used to store two 4-bit numbers A (a3a2a1a0) and B (b3b2b1b0) respectively. The input processor is used, when necessary, to convert A and B to an appropriate form or value. The 2-to-1 multiplexer is used to select either the carry from the full adder or an initial carry c0. Each of the four functions is executed serially by a full adder.
The ASM chart is given in Figure 2. A reset pulse will bring the processor to the initial state IDLE (T0) waiting for a "START" signal. Note that the reset signal should be 0 during the operations. The contents of registers R1 and R2 should remain intact while the processor is waiting to start. Operations will start when the signal "START" is 1. The first operation is to load the number A into register R1 in T0. In state T1, the second number B and an initial carry c0 are loaded respectively into register R2 and the D flip-flop. c0 depends on Op2 Op1 and is a conditional output. You need to complete the shaded box in the ASM chart for the function set assigned to you. The selected arithmetic operation is carried out serially in the following four states. The processor returns to the initial state after the completion of an arithmetic operation. The result is stored in register R1 and the contents in R2 should remain unchanged. Assume that the input "START" is “don’t care” after A is loaded into R1.
3IC Requirements
The maximum number of ICs that can be used in your design is eleven. They are given in the template for the schematic diagram. Note that the design is partially completed in the template.
4Description of ICs 74176 and 74194
IC 74174 contains six positive-edge-triggered D-type flip-flops. Unlike ICs 7474 and 7476 which have separate asynchronous preset and clear, all six flip-flops in 74174 have a single common active low asynchronous clear input and no preset input. Also note that the flip-flop outputs are single-rail.
IC 74194 is a universal shift register with four operating modes: synchronous parallel load, right shift, left shift, and do nothing. These modes are selected by two control signals, s1 and s0, and listed in Table 2.
Table 2 Function table for IC 74194.
s1 s0 / Mode / Outputs0 0
0 1
1 0
1 1 / Hold
Shift right
Shift left
Parallel load / QA QB QC QD
SRin QA QB QC
QB QC QD SLin
A B C D
The original contents of the register are QA QB QC QD. "SRin" is a serial data input to the leftmost bit in the operation mode "right shift". "SLin" is a serial data input to the rightmost bit when the contents of the register are shifted left. ABCD is the data loaded into the register in parallel. All modes are triggered at the positive transition of a clock input. An overriding clear is provided to clear the register regardless of the level of the clock.
A 6-state generator is used to generate the statesT0, T1,T2,T3,T4,and T5,. Note that control will not pass from T0 to T1 until START is 1. Therefore the system clock cannot be applied directly to the state generator. When the processor is in the initial state and START is 0, the state generatorremains in T0.The contents of the two shift registers and zi are intact.
5Design Procedure
(a)Design the input processor by completing the (short form) truth table in Table 3. Implementing the circuit using a 74153 IC.
(b)Determine the initial carry c0 from the truth table.
(c)Design the control circuit.
(d) Design the state generator.
(e)Draw a schematic diagram.
Table 3 Truth table for input processor.
Op2 Op1 / xi / yi / c000
01
10
11
6Simulations
Simulate each of the four arithmetic functions assigned to you given in the report template. Verify your simulation results using decimal numbers and hand-calculations. Provide an explanation if your simulation results are different from the hand-calculated decimal results.
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