AFEIIt Timing

and Triggering Modes:

Date: April 16, 2007

Kwame Bowie

  1. Introduction:

The AFEIIt will be used to integrate and digitize VLPC charge information for the MICE experiment. The core component of the AFEIIt board is the Trip-t application specific integrated circuit (ASIC) designed at Fermilab. The Trip-t chip incorporates circuitry that integrates and stores charge continuously until a trigger signal is received.Upon receipt of the trigger signal, the Trip-t chip’s stored chargemay be extracted and digitized.

The Trip-t chip is able to provide impressive channel density, but does so by requiring dead time. Using Tevatron Dzero timing (396 ns bunch spacing), the Trip-t chip has a “live” integration window of 100 ns during which charge from 32 channels are integrated and stored properly. For the remaining 296 ns, the input preamplifiers are in a “reset” mode and are not sensitive to incident charge pulses.

The AFEIIt board was designed with the assumption that the timing and triggering systems would shoulder the burden of ensuring that data is integrated and digitized at the proper instant. This assumption minimizes the burden on the AFEIIt board firmware, but it requires that the triggering and timing systems be carefully calibrated. The AFEIIt boards will function perfectly well with the timing and triggering relationships completely wrong. The only indication of a timing-triggering mismatchis that the associated data will be completely meaningless. There is an advantage of such a situation: it is relatively easy to ensure that each AFEIIt board is functioning properly and identically. The disadvantage is that the timing and triggering systems require a great deal of time and expertise to calibrate.

For the timing and triggering systems to operate properly, they must accomplish three (3) key tasks:

1)Must ensure that each Trip-t chip on each AFEIIt board integrates charge at the same instants.

2)Must ensure that each AFEIIt board receives and processes triggers from the same integration instant.

3)Ensure that cabling and waveguide delays are compensated such that the particles of interest arrive in the AFEIIt boards’ “live” integration windows.

  1. Timing System Background:

The timing system has the responsibility for providing the signals that will allow the AFEIIt boards to integrate charge at the precise instant that the particles of interest pass through the Trip-t inputs. The AFEIIt boards require two timing signals to properly accomplish this task: clock and 1st_xing. These two signals are used by the FPGA firmware to generate additional signals which define the time instants during which charge may be integrated and instants during which the Trip-t inputs are insensitive to charge pulses.

2.1 Integration Windows

The Trip-t chip is a device which stores integrated charge from many channels during several sampling instants. These sampling instants will be referred to as integration windows for the remainder of this document. There are a few constraints on the integration window locations due to the reset induced dead-time of the Trip-t chip. The Trip-t chip requires a certain amount of time for it’s preamplifiers to reset between storing integrated charge samples. The maximum rate that the Trip-t chip may be store integrated charge samples depends upon this preamplifier reset time. In most cases it is desirable to have a reasonably large sized interval during which the preamplifiers are not in the “reset” state and the Trip-t may accurately integrate charge. The window during which the preamplifiers are not in the “reset” state is called the “live” integration window. It is important to distinguish the “live” integration windows because charge is usually stored during both “live” and “reset” integration windows. However, it is important that the data which is extracted and digitized comes from only the “live” integration windows. Current testing utilizes a single AFE “master” board to generate the necessary timing signals for the other “slave boards. In this manner, multiple boards are able to synchronize their operation. The remainder of this section will discuss how full fledged timing systems must operate.

2.1.1DZero/Tevatron “Live” Integration Windows:

For the DZero project at Fermilab, the AFEIIt firmware was designed to incorporate the Tevatron superbunch structure. The addition of the superbunch structure to the FPGA code imposes a constraint that ensures triggers will not be processed during the gaps in the Tevatron beam structure. The DZero Tevatron firmware provides for 36 “live” integration windows grouped into three (3) superbunches. The superbunch structure repeats at the rate of the 1st_xing signal (every 21us). The “live” integration window for DZero is roughly 100 ns long and the spacing between live integration windows within the same superbunch is set at 396 ns. Initially all tests using the AFEIIt board will incorporate this Tevatron superbunch timing constraint. This constraint provides a suboptimal system for VLPC testing and MICE since there exists no such bunch structure for either case. The overall effect of the added superbunch constraint is to decrease the trigger efficiency/throughput of the system.

2.1.2MICE “Live” Integration Windows:

One of thegoals of the MICE AFEIIt firmware rewrite is to implement a more efficient integration window structure. The MICE “live” integration windows are expected to occur with 324 ns spacing, and an appropriately shorter “live” integration window width. The live integration windows will maintain a constant spacing for the duration of the spill. Each spill will last roughly 1 millisecond and will be separated by 1 second.

  1. Triggering System Background:

The AFEIIt board implements an integrated charge pipeline using the Trip-t chip. The data inside this pipeline may only be digitized upon the receipt of a trigger signal. The trigger signal selects which element in the integrated charge pipeline will be digitized and transmitted to the DAQ system. Let’s investigate the operation of the Trip-t pipeline.

3.1 Trip-t Pipeline:

The Trip-t chip implements a circular buffer of capacitors for storing integrated charge in an analog fashion. This circular buffer has a programmable depth with a maximum depth of 48 samples and is referred to as the pipeline. The pipeline is an integral part of the timing system and its inclusion enhances the Trip-t chip’s flexibility. The pipeline is critical because it provides a mechanism to compensate or cabling and electronics delays associated with trigger generation. It is very important that the pipeline be accounted for when calibrating the timing system.

The Trip-t pipeline stores data from a fixed period of time before the trigger signal arrives. If one were to think of the Trip-t chip as a device which saves a single sample from a fixed period of time before the trigger, then the pipeline depth defines that fixed period of time. The pipeline depth must be accounted for when generating a trigger signal to be sent to the AFEIIt boards. Even if the timing system generates its signal properly such that the particles of interest arrive at the Trip-t chips during the “live” integration windows, the trigger system must be set up to properly pick out the correct index in the Trip-t pipeline. If the proper index is selected, then the particles of interest may be properly digitized. If the improper pipeline index is selected, then the data will not represent the particle of interest.

3.2Development and Test Triggering Systems:

The following operational modes are to be used until the final MICE DAQ hardware, FPGA firmware, and software are available. These triggering modes have been used for previous LED runs, test stand measurements, and cosmic ray tests.

3.2.1 Self Triggered Operation:

The self-triggered solution allows the AFEIIt boards to automatically generate an L1Accept trigger and readout data if a discriminator value is detected above threshold during a “live” integration window. The self-triggered mode of operation requires no expertise for setting up the timing and triggering systems. The timing and triggering system for the self-triggered mode of operation is encompassed in a single ribbon cable placed between the 10-pin diagnostic ports of two AFEIIt boards with compatible firmware.

The self-triggered timing system implements a master-slave timing system, where the master board provides its clock and 1st_xingsignals to the slave board. From these signals, the slave boards is able to generate “live” integration windows at the same instant as they occur on the master board. The master board provides the 1st_xing signal to the slave board a few cycles early to allow for propagation delays. The triggering mechanism for the self-triggered mode is handled by two separate signals on the debug port. Each board may process an internal my_trigger signal or an external his_trigger signal. The my_trigger signal is delayed such that it arrives at the same instant as the his_trigger signal if both triggers are asserted.

The functionality of the self triggered signals has been tested exhaustively on a test bench. With the current ribbon cable and firmware, the timing accuracy is currently at +/- 5 ns on the 1st_xing signal between both boards. The trigger accuracy has been shown to have an accuracy of one-half of one clock tick or 9.4 ns.

3.2.2Fixed Particle LocationTriggerSystem (LED runs):

The fixed particle timing DAQ system is setup to incorporate an external trigger, and is the architecture that has been used for a majority of the LED runs. The LED runs have been set up such that the DG2020 places an LED pulse at a given “live” integration window within the first Tevatron superbunch. The external trigger must be timed such that it selects this unique “live” integration window from the pipeline. If the trigger does not correspond to the fixed “live” integration window, the value that is read back from the AFEIIt board will not be representative of the photon-induced charge liberation exhibited by the VLPCs as a result of the LED pulse.

To properly align the LED pulse and trigger, the 1st_xing signal is used as an absolute time reference. The 1st_xingsignal defines the “live” integration window locations in the current iterations of the AFEIIt firmware. The 1st_xing signal from the AFEIIt boards act as a trigger for the DG2020 to produce the LED and L1A signals. The proper timing of the system then becomes a two-step process:

1) The L1A trigger needs to be placed such that it corresponds to the correct “live” integration window.

2) The LED pulse needs to be placed at the optimal positionwithin the correct “live” integration window.

These two steps proved to require a reasonable amount of effort including a few firmware updates to provide debugging information. One must account for the cable delays from the DG2020 to and from the AFEIIt, the waveguide delays to the VLPCs, and the delays from the HP analog pulser module.

3.2.3 Random Particle Location TriggerSystem (cosmic ray runs):

The random particle locationtrigger system requires significantly more timing calibration effort than the fixed particle location situation. The random particle timing situation has been used for the cosmic ray data runs using the external trigger. The random particle location trigger system operates under the assumption that the arrival location of the cosmic ray particles with respect to the “live” integration windows will be random. In this trigger system, it is expected that some fraction of the particles of interest will arrive properly in the “live” integration windows and the rest will not. The goal of this triggering system is to create a mechanism by which only the particle that arrive in a “live” integration window are capable of generating a trigger.

The first step in calibrating the random particle location system is to provide the trigger system a signal that approximates the “live”integration window locations. Thisvalid_particle signal is generated by estimating the “live” integration windowson the AFEIIt boards and compensating for cable and waveguide delays. The valid_particle signal is used to veto the TOF trigger generated by beam monitors or PMTs. If the valid_particle signal is true, then the trigger is sent to the AFEIIt boards otherwise no trigger is sent. The calibration procedure for the valid_particle signal consists of sweeping the location of this signal until it coincides with the integration windows on the AFEIIt board. The tricky portion about this step is that there needs to be an offset from the AFEIIt integration windows that coincides with the cable and waveguide delays. To further complicate this step, there is no good feedback mechanism to see if the valid particle signal is placed correctly. The only way to be certain that the placement is correct is to analyze enough data to be confident that accumulated data represents real particles.

The next step in the random particle location trigger calibration is to generate the L1A trigger with the appropriate offset from the “live” integration window in which the particle arrives. This step of the procedure requires a delay module to generate a trigger with the appropriate amount of delay to account for both the Trip-t pipeline and any cabling or waveguide delays. This step is not too difficult because the valid trigger instants are fixed and well known. For this step, the trigger output must align exactly with the valid trigger instants and this timing may be easily checked with an oscilloscope.

3.3MICE Timing and Triggering System

The MICE timing and triggering systems designs are very similar to the random particle location situation. The primary difference is that all of the timing signals are derived from the ISISaccelerator and not a “master” AFE board. By operating in this fashion, there is no need for the AFE boards to return timing information to the timing and triggering systems. The removal of this feedback path reduces EMI, cabling requirements, and complexity.

However, the most important change between the MICE timing and triggering systems and those used during the cosmic ray tests lies inthe fact that the timing is derived from ISIS and not an AFE board. By using ISISbunch spacing to generate the timing system signals, the timing system dictates when charge is integrated. This situation is the opposite of the cosmic ray testing, where the AFE board selected arbitrary instants to integrate charge. The cosmic ray test situation is not optimal for MICE because particles will very likely arrive within certain timing constraints. If this information is mot incorporated into the timing system, the efficiency and throughput of the DAQ system will be much lower than desired. It is necessary to synchronize the AFE boards’ integration windows to the ISISparticle bunches to ensure that interesting particles are not ignored simply because the Trip-t amplifiers are in “RESET”.