PC Based Spectrum Analyzer Phase III
Design Report
May03-10
Client: Teradyne Corporation
Faculty Advisor: Degang James Chen
Team Members:
Paul Heil
Aung Thuya
Eric Rasmussen
Michael Cain
November 19, 2002
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Table of Contents
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1.1 Abstract
1.2 Acknowledgement
1.3 Definition of Terms
2.1 Introduction
General Background
Technical Problems
Operating Environment
Intended Users and Uses
Assumptions and Limitations
2.2 Design Requirements
Design Objectives
Functional Requirements
Design Constraints
Measurable Milestones
2.3 End Product Description
2.4 Approach and Design
Technical Approaches
Technical Design
Testing Description
Risk Management
Recommendation for Continued Work
2.5 Financial Budget
2.6 Personal Effort
2.7 Project Schedule
3.1 Project Team Information
Project Client
Project Advisor
Team Members
3.2 Summary
3.3 References
List of Figures
Figure 1: Design block diagram...... 4
Figure 2: Overall amplifier design...... 7
Figure 3: DC offset correction...... 8
Figure 4: Frequency response calibration...... 9
Figure 5: Project schedule...... 13
List of Tables
Table 1: Design specification...... 10
Table 2: Financial budget...... 11
Table 3: Personal budget...... 12
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1.1 Abstract
The purpose of this project is to develop an amplifier for Teradyne Corporation. This will constitute Phase III of an ongoing project for Teradyne. It is to be a 100 MHz high gain, low noise, and low distortion amplifier with DC offset correction and frequency response calibration. To accomplish this, the design team will research various amplifier topologies and DC offset correction and frequency response calibration schemes to design the amplifier. Teradyne will use this device as a pre-amplifier for the spectrum analyzer developed in Phase I and Phase II.
1.2 Acknowledgement
The design team would like to thank Teradyne Corporation for providing a team of experts who will contribute knowledge to the project as well as financial support.
We would also like to thank our faculty advisor Degang James Chen whose expertise will be invaluable in the future of this project.
Thank you!
1.3 Definition of Terms
Analog — A signal that changes continuously and is not limited to discrete values.
A/D Converter — analog-to-digital converter — The conversion of an analog signal to a digitally sampled signal.
DC offset — given signal source does not have the correct 0-crossing, and is shifted either up or down from there.
Digital — A signal that has discrete values, namely one or zero.
DSP — digital signal processing — Computer manipulation of analog signals (commonly sound or image) which have been converted to digital form.
Dynamic range — The maximum difference in amplitude between the fundamental and harmonic frequencies (measured in dB).
Fundamental frequency — The harmonic component of a complex wave that has the lowest frequency and commonly the greatest amplitude.
Harmonics — Signals that are integer multiples of the fundamental frequency.
High gain — The ratio of the output amplitude to the input amplitude is very high.
Interfacing — Providing communication lines between different parts of a system.
Low noise and low distortion — A low occurrence of undesired signals and interference.
Low pass filter — A filter that will pass low frequencies up to a point, which is called the corner frequency, after which all frequencies are blocked.
SAR — successive approximation register — analog-to-digital converter that uses a binary search algorithm to converge on the input signal.
SNR — signal-to-noise ratio — Ratio of the amplitude of the desired signal to the amplitude of any noise.
Spectrum analyzer — A computer based tool that analyzes signals in the frequency domain.
THD — total harmonic distortion — The ratio between the power of all harmonic frequencies above the fundamental, to the power of the fundamental frequency.
2.1 Introduction
General Background
For Phase III of this project, the design team will create a pre-amplifier for the spectrum analyzer created in Phase I and Phase II. The pre-amplifier will condition the input signal to the spectrum analyzer meeting noise and distortion requirements. The device is required to amplify signals of up to 100MHz.
Technical Problems
The system will consist of two operational amplifiers in resistive feedback. The configuration will maximize bandwidth while maintaining low noise and low distortion. The DC offset correction scheme will automatically keep the DC offset voltage below 1mV. Noise and distortion requirements will be fulfilled by carefully selecting components and meticulously laying out the PC board. The frequency response calibration scheme must condition the output signal to meet frequency response flatness specifications.
Operating Environment
The system will be used in a climate-controlled laboratory at room temperature with low humidity. There will not be much variation in temperature and other environmental factors.
Intended Users and Uses
The Teradyne Corporation engineers are the sole intended users of this system. They plan to use the fully assembled spectrum analyzer to test silicon chips in their laboratories. The system will serve a basic building block and be duplicated many times.
Assumptions and Limitations
The design team assumes that:
- The Teradyne engineers are familiar with the operation of a spectrum analyzer.
- Appropriate parts can be acquired at a reasonable price and in reasonable quantities.
- The pass-band of the amplifier meets frequency response flatness requirements.
- The input will only consist of signals from DC to 100MHz at the appropriate voltages.
- Necessary testing equipment will be made available.
The design team’s limitations are:
- For low distortion, a high open loop gain is needed, which causes more noise.
- The phase margin of the gain bandwidth of the amplifier must be stable.
- Component limitations such as thermal noise from resistors and flicker noise from active devices.
2.2 Design Requirements
Design Objectives
Figure 1: Design block diagram
Overall design — The design objective is to develop a pre-amplifier with DC offset correction and frequency response calibration.
Operational amplifier — The AD8021 operational amplifier from Analog Devices was selected because it met output signal swing, distortion, open loop gain, and bandwidth requirements.
DC offset correction — An automatic scheme that corrects the DC offset to 1mV has been designed. A monotonic 18-bit DAC from Analog Devices was chosen to correct the offset voltage. A programmable logic device will be used to successively zero the DC offset.
Frequency response calibration — The amplifier configuration is ideal for DC gain and pole-Q calibration because they are independent of one another. It is assumed that the pass-band of this amplifier is flat enough to meet the frequency response flatness requirement. This assumption is valid because of more than adequate open loop gain. A programmable logic device will be used to successively calibrate the DC gain then the roll off flatness.
Functional Requirements
Wide input frequency range — The amplifier will be able to amplify signals from DC to 100 MHz.
Low noise and low distortion — The amplifier will be able to meet noise and distortion requirements.
Programmable gain settings — The amplifier will have programmable gain settings for the specified frequency range.
DC offset correction — The DC offset correction can be turned on and off.
Design Constraints
Parts constraint — High quality, precision parts are required to obtain the specified design requirements for noise and distortion.
Bandwidth constraint — Amplification of signals up to 100MHz requires op amps with large bandwidths and near 90˚ phase margin.
Cost constraint — Teradyne has promised our team $3000 to complete our project.
Measurable Milestones
Schematic level implementation — Design of the device at the schematic level coupled with Spice simulations to verify functionality and design requirements.
PC board layout — The device must be carefully laid out onto a PC board. The group must take every necessary step to minimize parasitic inductances and line-to-line signal interference.
Fabrication — The device will be fabricated onto a PC board though an outside contractor.
Testing — The final product will be tested guaranteeing it meets all specified design requirements.
Finalize — All data will be assembled into a final report. The product will be delivered to Teradyne.
2.3 End Product Description
The PC based digital spectrum analyzer will be used with Teradyne Corporation’s Integra J750 Enhanced Digital Channel Board, a machine used to test large number of digital chips for other companies. The amplifier produced by our team will serve as a pre-amplifier to the spectrum analyzer. The amplifier will be able to amplify a signal of up to 100MHz. It will have a number of discrete gain settings; programmable by dipswitches on the board. The amplifier will meet noise, distortion, and DC offset voltage specifications.
2.4 Approach and Design
Technical Approaches
The team’s approach to this problem is to first research various textbooks and papers for maximum bandwidth op amp configurations, DC offset correction methods, and frequency response calibration schemes. Schematics of the device will be created in Cadence. Spice simulations will be used to verify functionality and design specifications. PC board layout will be accomplished using software provided by Teradyne. Companies such as Analog Devices will be employed to fabricate our device onto a PC board. Testing will be completed at Iowa State University and Teradyne facilities.
Technical Design
Programmable gain — The amplifier’s gain will be programmable with a specified number of settings. The schematic of the amplifier configuration is shown in Figure 2. Digital potentiometers will be used to generate the discrete gain values. The equations that follow Figure 2 prove that the amplifier configuration has maximum bandwidth.
Figure 2: Overall amplifier design
DC offset correction — The DC offset correction will be implemented by using a monotonic 18-bit DAC employing a programmable logic device to successively zero the offset. Figure 3 shows the schematic of the DC offset correction.
Figure 3: DC Offset Correction
High bandwidth — The high bandwidth specification will be accomplished through the use of a configuration of two op-amps and resistor feedback. This configuration essentially has three times the bandwidth of single amplifier configurations.
Frequency response calibration — The frequency response flatness will be calibrated through the use of Miller compensation, operational amplifier configuration, and a programmable logic device. Figure 4 shows the frequency response calibration schematic.
Figure 4: Frequency response calibration
Testing Description
Testing will be completed at Iowa State University and Teradyne facilities. Equipment from the subsequent facility will be used. The team’s biggest problem will be obtaining the spectral clarity needed for the input signal. The solution will be two fold. A sinusoidal wave at low frequencies will be produced by a 22-bit - DAC. At high frequencies, a high quality ring oscillator will be used. To obtain accurate THD and noise measurements, a high quality spectrum analyzer will be used to perform the spectral analysis. Specific acceptance requirements are given in Table 1.
Table 1: Acceptance Criteria
Input / TotalInput / Voltage / Available / Max Output / Freq Response / Harmonic
Frequency / Range / Gain Settings / Voltage / Flatness / Distortion / Noise
Range / (Volts) / (dB) / (Volts) / (dB) / (dB) / (nV/rtHz)
DC — 1kHz / +/- 5 volts / 6, 20, 40, 60 / +/- 10 volts / 0.05 dB / < - 105 dB / 1.5 nV/rtHz
> 1kHz - 20 kHz / +/- 5 volts / 6, 20, 40, 60 / +/- 10 volts / 0.05 dB / < - 95 dB / 1.5 nV/rtHz
> 20kHz - 100kHz / +/- 2.5 volts / 6, 20, 40 / +/- 5 volts / 0.10 dB / < -85 dB / 2.5 nV/rtHz
> 100kHz - 1MHz / +/- 2.5 volts / 6, 20, 40 / +/- 5 volts / 0.10 dB / < - 80 dB / 3.5 nV/rtHz
> 1MHz - 10MHz / +/- 2.5 volts / 6, 20, 40 / +/- 5 volts / 0.10 dB / < - 70 dB / 3.5 nV/rtHz
> 10MHz - 20MHz / +/- 2.5 volts / 6, 20 / +/- 5 volts / 0.10 dB / < -65 dB / 3.5 nV/rtHz
> 20MHz - 50MHz / +/- 1.0 volts / 6, 20 / +/- 2.0 volts / 0.10 dB / < -50 dB / 5.0 nV/rtHz
> 50MHz - 100MHz / +/- 1.0 volts / 6, 20 / +/- 2.0 volts / 0.10 dB / < -40 dB / 5.0 nV/rtHz
Risk Management
The biggest risk for this project is not having the necessary parts. There is the possibility that they will not arrive on time or function properly. In order to obtain the required parts when needed, the team will place orders for needed parts a soon as is possible. If parts do not arrive on time the team will shift its focus to another part of the project that is not constrained by the late parts. The design team will minimize the risk of receiving faulty or broken parts by ordering extra parts. Most of our parts are inexpensive and a number of PC boards could be ordered. The PC board could cost upwards of $3000 dollars, but the majority of that cost is in development and not in production.
Losing a team member and falling behind schedule is another risk. To minimize the effect, it will be imperative that all team members have a working knowledge of every part of the design.
Recommendation for Continued Work
The design team recommends that the project be completed as designed, with the exception of the noise requirements. The current design will have much higher output noise than is desired because the noise requirements are difficult to reach. However, solutions to meeting the requirements are still being researched. All other design requirements have been met in simulations.
2.5 Financial Budget
Table 2: Financial Budget
Item / Original Estimated Cost / Revised Estimated CostBoard Fabrication / $2000 / $2000
Components / $1000 / $1000
Project Poster / $100 / $48
Total Estimated Cost / $3100 / $3048
Table 2 represents the estimated cost of the parts needed to complete the pre-amplifier, and other aspects of this project. Teradyne will fund the cost of materials and can assist in or do any required board layout. They will provide funding for this project minus the cost of the poster, which was purchased by the design team.
2.6 Personal Effort
Table 3: Personal Budget
Team Member / Original Estimated Effort / Revised Estimated EffortMichael Cain / 205 / 185
Paul Heil / 210 / 190
Eric Rasmussen / 200 / 230
Aung Thuya / 195 / 195
Total Estimated Effort / 810 / 800
Table 3 shows the design team’s personal budget. The design team plans to meet twice a week throughout the duration of the project. One meeting will be with Dr. Chen, and the other will be as a team. There are ten weeks left in the fall semester and sixteen in the spring semester. Assuming the meetings with Dr. Chen is one hour and the team meetings are two hours, each member will spend a total of 78 hours in meetings alone. The remaining time will be spent individually or in a group. An estimated 810 hours will be needed to complete the project.
Each member will be working in the following areas.
Michael Cain — Research and design frequency response correction schemes, find and research
components, document speed versus accuracy trade offs.
Paul Heil — Research and design DC offset and frequency response correction schemes, find and
research components, document speed versus accuracy trade offs.
Eric Rasmussen — Research op amp topologies, design amplifier, run simulations, document
noise versus distortion trade offs.
Aung Thuya — Research op amp topologies, design amplifier, run document noise versus
distortion trade offs.
Each member will test and verify the board after fabrication.
2.7 Project Schedule
Figure 5 shows the design team’s projected project schedule.
Figure 5: Project Schedule
3.1 Project Team Information
Project Client
Michael McNally
781-999-8480 (phone)
888-594-7958 (pager)
Teradyne
Integra Test Division
26 Crosby Drive
Bedford, MA 01730
Lee Moore
781-999-8131 (phone)
888-740-7291 (pager)
Teradyne
Integra Test Division
26 Crosby Drive
Bedford, MA 01730
Project Advisor
Degang James Chen
515-294-6277
Fax: 515-294-8432
329 Durham
Electrical and Computer Engineering
Iowa State University
Ames, IA 50011
Team Members
Michael Cain
515-268-1847
320 Hillcrest Apt 16
Ames, IA 50014
Cpr E
Paul Heil
515-231-5996
616 Billy Sunday Road
Ames, IA 50010
Cpr E
Eric Rasmussen
515-572-3091
3420 Wilson Hewitt
Ames, IA 50013
EE
Aung Thuya
515-572-7820
4335 Frederisksen Court
Ames, IA 50010
EE
3.2 Summary
The demand for sophisticated test equipment will grow as the integrated circuit industry grows. As companies attempt to produce larger volumes of integrated circuits, new test equipment will be needed to match this volume. The digital spectrum analyzer will enable Teradyne Corporation to test and monitor integrated circuits quickly, efficiently, and accurately.
3.3 References
Analog Devices AD8021 operational amplifier specification sheet -
PIC 18C Series Microcontroller specification sheet-
Randall L. Geiger, "Amplifiers with maximum bandwidth", IEEE Trans. Circuit Syst., vol. CAS-24, pp. 510 - 512, September 1977.
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