DDR SDRAM Controller Core


Product Description 1.0

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Features

  • Single chip DDR SDRAM controller in a Xilinx Virtex II FPGA
  • Generic bus interface to common microprocessors or PCI bus
  • Data rates up to 200MHz
  • Supports 128/256/512Mbit DDR SDRAMs
  • Programmable burst lengths 2,4 and 8
  • Programmable CAS latency 1.5,2.0,2,5 and 3.0
  • Programmable timing parameters tRP, tRCD and tRFC.
  • Programmable refresh counter for automatic auto refresh.
  • Read and writes without auto pre-charge
  • Optional address pipelining
  • Support for Four internal banks
  • Pre charge all with A10
  • Parameterized address and data bus widths
  • Adheres to JEDEC specifications.
  • Supports devices from all major vendors
  • Extensive verification suites for functional and post layout verification

AllianceCORE Facts
DDR SDRAM Controller
Core Specifics
Device / XC2V250-FG456-5
CLB s Used / 97/384
SLICEs Used / 388/1536
IOBs Used / 176/200
Operating Frequency / 100 MHZ
Device Features used / Digital Clock Managers: 2/8
Supported Devices
XC2V250-FG456-4, 5
XC2V500-FG456-4, 5
Provided with Core
Documentation / Core User Guide
XC2V250 Datasheets
Design File Formats / Verilog Source code
Verification Tool / Verilog XL 3.20
Constraint Files / User Constraints file
Design Tool Requirements
Xilinx Core Tools / Design Manager 3.3
Entry/Verification Tools / Verilog XL 3.20
Synthesis Tools / Synplicity’s Synplify 6.2.4
Support
Support provided by Comit Systems, Inc.

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Figure 1. DDR SDRAM Controller system Block Diagram

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Recommended Design Experience

Knowledge of bus interface and DDR SDRAM is required. The user must be familiar with HDL design methodology in a hierarchical design environment.

General Description

The DDR SDRAM controller can be used for interfacing microprocessors/PCI local bus with DDR SDRAM. It converts the CPU/PCI address/data cycles into DDR SDRAM cycles. Controller is designed in such a way that all the timing and device parameters are programmable.

Functional Description


The DDR SDRAM controller core is partitioned into three major modules namely Bus Interface, Finite State Machine and Auto Refresh Generator.

Bus Interface

This module interfaces with microprocessor or PCI local bus. It decodes cycles on the bus and presents it to DDR SDRAM Controller. It presents datapath and control signals to and from DDR SDRAM controller.

Finite State Machine

This is the heart of the DDR SDRAM Controller and drives all the commands, control signals and address to the DDR SDRAM

Auto Refresh generator

Refresh is done using CBR (auto-refresh). DDR SDRAM Controller does refresh once every 15.625us.This interval is programmable interms of clocks.

Verification methods

The DDR SDRAM controller has been tested extensively using the testbench developed at Comit Systems. The testbench is also available with the core.

Comit Systems, Inc.

3375 Scott Blvd. Ste 139

Santa Clara, CA 95054, USA.

Phone: +1 (408) 988-2988

URL:
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