Homework 07 due Wednesday 9/24/08
Turn in your source code (with changes highlighted) and your simulation waveform. See HW 07.zip for files.
- Complete the file tb_p1.vhd. Hint: This can be done with a single line of VHDL code. The correct waveform is shown below.
------
-- tb_P1.vhd
-- Write an expression for A to produce the output
-- shown in the provided waveform. S is the control signal.
-- A is updated every 10 ns. If S = "00", A does not change.
-- If S = “11” we don’t care what happens to A.
-- When S = "01" or "10" A counts in the sequences shown below:
-- S = "01" S = "10"
-- 00 00
-- 01 10
-- 11 11
-- 10 01
-- 00 00
-- ......
------
LIBRARY IEEE; USE work.all;
USE IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TB IS END ENTITY TB;
ARCHITECTURE TEST OF TB IS
SIGNAL A: unsigned(1 downto 0) := "00";
signal S: unsigned(1 downto 0) := "01";
BEGIN
S <= S + 1 after 50 ns when S < "10" else "00" after 60 ns;
-- A <= ??? after 10 ns;
END ARCHITECTURE TEST;
- The equations below can be used to implement a mod 10 counter using D-flip-flops clocked by the rising edge of the clock.
Use four instances of the dff entity given in file flipflops.vhd and complete the file tb_p2.vhd. Run a simulation to verify that a mod 10 counter has been implemented. Note that the generate statement is used to instantiate four instamatics of the D flip-flop.
-- tb_P2.vhd
LIBRARY IEEE; USE work.all; USE IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TB IS END ENTITY TB;
ARCHITECTURE TEST OF TB IS
SIGNAL CLK: std_logic := '0';
Signal Q: unsigned(4 downto 1);
Signal D: unsigned(4 downto 1);
Signal C: unsigned(4 downto 1);
BEGIN
FF: for I in 1 to 4 generate
begin
U: entity dff port map(D(i), C(i), Q(i));
end generate;
CLK <= not CLK after 5 ns;
C(1) <= CLK;
D(1) <= not Q(1);
-- Add your equations here.
END ARCHITECTURE TEST;
- A four-bit shift register is shown below. Complete the architecture for this shift register.
An entity and incorrect architecture for this shift register is provided in the file sr.vhd. Change only the architecture so that the shift register is modeled correctly. Maintain the intent of the provided architecture. For example do not resort to a structural description of the architecture that requires intendances of flip-flop components. Use the provided file tb_sr.vhd to test your version of the shift register. The expected waveform is shown below.
-- SR.VHD 4 bit shift register
LIBRARY IEEE;
USE work.all;
USE IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SR IS
PORT
( CLK: in std_logic;
Din: in std_logic;
Q: OUT std_logic_vector(3 downto 0));
END ENTITY SR;
Architecture behav of SR is
begin
process(clk) is
begin
if CLK'EVENT AND CLK = '0' then
Q := Din & Q;
end if;
end process;
end architecture behav;
- Create a test bench and architecture for the BCDINC entity shown below. When RES = ‘1’ then BCDCNT is asynchronously reset to all 0’s. When RES = ‘0’ BCDCNT is incremented in BCD on the rising edge of CLK if EN = ‘1’. For example if BCDINC = 019916 before the enabled rising edge of the clock, after the rising edge of the clock the value will be 020016. When BCDCNT reaches 999916 the count stops and remains at 999916 until reset to 000016. Turn in a hardcopy of both the architecture and your test bench. Include enough snapshots of the simulation waveform to show that the architecture is correct.
LIBRARY IEEE;
USE work.all;
USE IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BCDINC IS
PORT
(
CLK: in std_logic;
EN: in std_logic;
RES: in std_logic := '1';
BCDCNT: OUT std_logic_vector(15 downto 0) := x"0000"
);
END ENTITY BCDINC;