2/11/2018, 2/19/2012 (revised Q#2 due date)
EE354L HW#8A ("Individual Effort" assignment) -- 3 questions with 4 sets of due dates
Directory of all files (.pdf .wmv .zip .txt) dir ( )
Assignment pdf (only the first 6 pages):exercises.pdf( )
combined zip file for all 4 parts: ee201_RTL_exercises.zip ( )
Alldue dates are before the midterm. Note: Q#2 is due first and it is before the quiz.
Late submission is allowed for online submission (not for paper) for up to 3 days for flat penalty of 3%.
Q2.pdf Q2.wmv
Q#2 paper (draft) submission: In class on Wednesday 2/14/2018 at 10:05 AM and on Thursday 2/15/2018 at 12:05 PM.
Draft submission is not graded.
Q#2 online submission: 11:59PM Friday 2/16/2018 online
Q#2 late online submission: 11:59PM Tuesday 2/20/2018 online(no 3% penalty until 11:59PM on Monday 2/19/2018)
Q#2 paper submission: In class on Tuesday 2/20/2018 by 12:05PM and onWednesday 2/21/2018by 10:05 AM.
Q1.pdf Q1.wmv
Q#1 paper (draft) submission: In class on Wednesday 2/28/2018 at 10:05 AM and on Thursday 3/1/2018 at 12:05 PM.
Draft submission is not graded.
Q#1 online submission: 11:59PM Friday 3/2/2018 online
Q#1 late online submission: 11:59PM Monday 3/5/2018 online
Q#1 paper submission: In class onMonday 3/5/2018by 10:05 AM and on Tuesday 3/6/2018 by 12:05PM.
Q3.pdf Q3.wmv(for both parts of the Q#3)
Q#3 Part 2 paper (draft) submission: In class on Wednesday 3/7/2018by 10:05 AM and on Thursday 3/8/2018 at 12:05 PM.
Draft submission is not graded.
Q#3 Part 2 online submission: 11:59PM Friday 3/9/2018 online
Q#3 Part 2 late online submission: 11:59PM Monday 3/11/2018 online
Q#3 Part 2 paper submission: In class onMonday 3/19/2018by 10:05 AM and on Tuesday 3/20/2018 by 12:05PM.
Q#3 Part 1 paper (draft) submission: In class on Wednesday 3/21/2018by 10:05 AM and on Thursday 3/22/2018 at 12:05 PM.
Draft submission is not graded.
Q#3 Part 1 online submission: 11:59PM Friday 3/23/2018 online
Q#3 Part 1 late online submission: 11:59PM Monday 3/26/2018 online
Q#3 Part 1 paper submission: In class onMonday 3/26/2018by 10:05 AM and on Tuesday 3/27/2018 by 12:05PM.
Procedure
The procedure of simulating in Modelsim and submitting online is illustrated in a 44-minute webcast:pdfavitxt
Complete long weblinks for the above three:
Do not submit non-working Verilog files. We will consider such submission as an attempt to cheat.
You can easily verify if your results are right or not, by reading the test results.
All documents are posted here:
Besides the assignment (.pdf), we have posted, the lecture slides (.pdf files), short webcasts (.wmv files, all 4 together make 60 minutes), and a .zip file containing five file-folders (each with verilog codes and .do files for modelsim simulation).
Please download all the files. Unzip the .zip file in your C:\ModelSim_projectsfolder to form 4 project directories. Note: Since question #3 has two implementations, there are two folders for the same; all together 4 folders.
Absolutely no cheating please. This is an individual assignment. If you need help, we the teaching team members can quickly help you if you come with your hand-drawn state diagram.
Office hours: Gandhi and Pratush can help with all aspects of this homework. The TAs will only help with running Modelsim and with online submission procedure.
To provide you nearly unlimited help, I have requested the EE457 TAs and Mentors to help you during their on-campus office hours as shown below in PHE330:
Office hours of EE457 TAs and Mentors inPHE330:
Step-by-step procedure of simulating in Modelsim and submitting online
1. For each question, go through the question,go through the lecture slides (.pdf file) andthe webcast (.wmv file).
2. Complete paper design.
3. Fill up the few "// ** TODO **complete RTL Operations and State Transitions" sections in the core design.
4. Set up modelsim project, and simulate using the given testbench and .do file.
example: VSIM> do largest_num_divisible_by_7.do
5. Look at the waveforms produced and the results file, output_results.txt.
6. Do not start coding before you complete the state diagram on paper. Your first design may not be the right and you may have to modify. But revise your paper design first and then the Verilog code. Many students start fixing the Verilog code and they do not realize simple mistakes that would be apparent if they do the paper design first.
Please start early as many students find Q#1 and Q#3 quite difficult.
7. The paper submission(s): Please completethe questions in the assignment itself. Submit it in class.
Solutions will be distributed in class.
8. Online submission: Please submit the completed Verilog code file for the core design and the output_results.txt online using your UNIX account. Details of the submission procedure have been posted at:
The four commands are:
submit -user ee201 -tag ee201_make_A_close_to_B make_A_close_to_B.v output_results.txt names.txt
submit -user ee201 -tag ee201_largest_num_divisible_by_7 largest_num_divisible_by_7.v output_results.txt names.txt
submit -user ee201 -tag ee201_copy_array_to_array_imp1 copy_array_to_array_imp1.v output_results.txt names.txt
submit -user ee201 -tag ee201_copy_array_to_array_imp2 copy_array_to_array_imp2.v output_results.txt names.txt
9. Read the following file and look for your name in the congratulations file a couple of days after.