GaN-on-Diamond Wafers: Recent Developments

Felix Ejeckam, Daniel Francis, Firooz Faili,

Frank Lowe, Daniel Twitchen, and Bruce Bolliger

Element Six Technologies, US Corporation, 3901 Burton Drive, Santa Clara, CA 94054 USA

Phone: (408) 986-2439 Email:

Introduction

GaN-on-Diamond wafers and transistors have emerged as a leading technology for use in next generation radar and other microwave defense applications. This is due to diamond's excellent thermal properties. However, accurate measurement of the thermal properties of GaN-on-diamond wafers is challenging, and wafer properties such as gate leakage have not been previously optimized and reported in the literature. This paper reviews state-of-the-art techniques and results of the thermal measurements, as well as progress towards delivering 100mm wafers that meet all target wafer specifications.

Purpose

GaN-based transistors and their related RF Power Amplifiers (PAs) have emerged as the leading solid-state technology to replace traveling wave tubes in radar, EW systems, and other defense-related applications. However, significant thermal limitations prevent GaN PAs from reaching their intrinsic performance capability. GaN-on-Diamond technology has previously been introduced by the authors [1,2] as a viable approach for enabling GaN such that the thermal limitation is significantly diminished, and areal RF power densities can triple compared to GaN-on-silicon carbide.

Figure 1 summarizes the process steps used to fabricate GaN-on-Diamond wafers. Starting from the {111} silicon (Si) substrate, the epitaxial layers include a 1.2 µm thick transition buffer; a 800 nm thick GaN buffer layer; a 17 nm thick AlGaN Schottky barrier, and a 2 nm GaN cap layer. In forming GaN-on-Diamond, the GaN-on-Si is first bonded to a temporary carrier, the Si substrate and transition layers are etched away, a 30 nm dielectric is deposited onto the exposed AlGaN/GaN, 100 µm thick CVD diamond is then grown directly onto the dielectric beneath the AlGaN/GaN epitaxy, and then finally the temporary carrier is removed (see Figure 1). The resulting GaN-on-Diamond wafer is then mounted to a 500 µm thick carrier to enable it to go through the device fabrication process steps.

Figure 1. The flow diagram summarizes the general approach to making a GaN-on-Diamond wafer.

Measuring thermal properties to understand how much the GaN-on-Diamond technology diminishes the thermal limitations of standard GaN semiconductor technology is challenging. For instance, accurately measuring the thermal conductivity of the diamond within a few microns adjacent to the GaN buffer is quite different than measuring the diamond’s bulk thermal conductivity. And separating the TBR (thermal barrier resistance) of the diamond near the GaN buffer from the TBR of the interface layer between the diamond and GaN buffer is also difficult. Various measurement techniques, including Raman thermography and time-domain thermal reflectance, have been used to meet these challenges. This paper reviews the state-of-the-art techniques for measuring thermal conductivity and TBR.

One hurdle is routinely faced by fab engineers and technicians who develop transistors and PAs with 100mm GaN-on-Diamond: gate carrier leakage often revealed after the top-surface SiN cap protection layer has been removed. Surface gate leakage can reduce a device’s power added efficiency.

What specific results were obtained?

In this work, the authors review the latest techniques for measuring thermal properties of state-of-the-art GaN-on-diamond technology, and summarize the most recent measurements of thermal properties of this new GaN technology. The authors use these recent measurements to predict the potential for further advancements in the thermal properties of GaN-on-diamond.

The authors also present a survey of recent technical challenges published by GaN-on-Diamond device makers. One challenge includes reports of gate carrier leakage on the GaN-on-Diamond wafer. The authors present state-of-the-art wafer measurements that show that the aforementioned challenge has been addressed.

References

  1. F. Ejeckam, D. Babic, F. Faili, D. Francis, F. Lowe, Q. Diduck, C. Khandavalli, D. Twitchen, and B. Bolliger, “3,000 Hours Continuous Operation of GaN-on-Diamond HEMTs at 350C Channel Temperature”, accepted to Semi Therm 2014 Conference in San Jose, CA.
  2. D.C. Dumka, T.M. Chou, D. Francis, F. Faili, and F. Ejeckam, “AlGaN/GaN HEMTs on Diamond Substrate with over 7 W/mm Output Power Density at 10GHz”, accepted to IEE Electronics Letters (Issue #20, 2013). See also: G.D. Via, J.G. Felbinger, J. Blevins, K. Chabak, G. Jessen, J. Gillespie, R. Fitch, A. Crespo, K. Sutherlin, B. Poling, S. Tetlak, R. Gilbert, T. Cooper, R. Baranyai, J.W. Pomeroy, M. Kuball, J.J. Maurer, and A. Bar-Cohen, “Wafer-scale GaN HEMT Performance Enhancement by Diamond Substrate Integration” at ICNS-10, 23-pages, August 27, 2013