EECS 141: Digital Integrated Circuits – Fall 2012

Report Cover Sheet

TERM PROJECT: FPGA SliceL

Report 3 – Putting it all Together and Optimization

Due Friday, December 7, 2012 by 5:00pm in the drop box.

Names
Description of Optimization Objectives
(You should describe what your optimization goals were here: e.g., minimum power, maximum speed, good balance of speed/area, etc.)
Parameter / Value / Units
SRAM Cell Area / µm2
Calculated Decoder Delay / ps
Simulated Decoder Delay / ps
Calculated Vertical Logic Delay / ps
Simulated WL to BL delay / ps
Simulated Vertical Logic Delay / ps
Total Simulated Delay / ps
Calculated Power Dissipation / µW
Simulated Power Dissipation / µW
Total Area / µm2
GRADE
Approach, result and correctness (65%)
Report (35%)
TOTAL

Complete SliceL Design

(Annotated schematic or block diagram and layout of the complete SliceL. Simulation showing representative operation with worst-case delay and timing of critical signals, including any clocks you used. You should provide highlights of the key optimizations/design decisions you made here - e.g., using domino logic in the decoders, reducing the supply voltage for the SRAM, etc.)

SRAM Cell Design

(Schematic and layout of the SRAM cell. Read and write margins/butterfly plots. You can skip this section if you did not modify the SRAM cell we gave you, but otherwise you should explain any changes you made from the design given to you in phase 1. )

Decoder/Vertical Logic/MUX Design & Read Delay

(Annotated schematics with gate sizes and layout of the decoder and vertical logic.Simulation showing worst-case propagation delay from the input of the decoder to the output of the SRAM array, hand calculation of the decoders’ and Vertical Logic delay and power. Explain your design decisions and approach. You do not need to provide transistor level schematics of any standard gates you used, but you should provide schematics of any new/non-obvious gates.)

Peripheral Circuits

(Schematic and layout of the SRAM peripheral circuits. Delays of the precharge and pull-downoperations. You can skip including the schematic and layout if you did not change the peripheral circuits that we gave you. You should however include the precharge and pull-down delays and verify that they are less than the critical path delay through your decoder. )

Appendix

(This space has been provided for you to include relevant information that did not fit into the previous sections. This is a good place to put any additional analyses you did that didn’t fit or you weren’t sure where to put. For example, you might provide a more detailed power break-down/estimate of each of the major blocks, logical effort sizing calculations of the complete decoder/vertical logic path, output buffer/multiplexor sizing, etc.)