The October and November Issue of Chip Design Will Showcase the Open Core Protocol International

Contents Report for May, June, July CD10/11/20181

Editorial Report“E” for May/June (?)Chip Design

PlannedTheme: “Chip/Package/Board” or “Low Power”

Editorial Topics: Embedded SOCs, Nanotech Tools, DFM/DFY, Power Arch, Programmable HW, System Languages, semi-Metrology, IP Metrics

TOC—jimk, needs update again for new order (1 page)

Editor’s Note (1 pg) – JB (done)

Reader Wants Print, not Links

Chip Design Online (1 pg)—need editing for length

In the News -- People in the News(2 pages), done

Product News ( pgs)--Not planned

Max’s Chips & Dips column (1.5), done

“Max's Chips and Dips: The Way Things Were

Behind the Numbers (2 pgs)--done

“”FPGA Vendors Throw Kitchen Sink at Power-Consumption Issues”, By Brian Fuller

Viewpoint – TopView (1 page)done

“A System-Level View of IP Integration,” by Jauher Zaidi, Palmchip Corporation

Focus Report (2 pagd)done

Smaller, Faster and More Parasitic, By John Blyler and Pallab Chatterjee

Editorial Feature—3D Packaging (1.5) need bio and headshot

The Impact of 3D Packaging, By Ann Steffora Mutschler

Editorial Feature—Quality (2.5) done

Making Quality a Top Priority in Next-Generation Designs, By Cheryl Ajluni

Editorial Feature—Custom IC (1.5) done

Custom IC Design: They Call This Progress? By Ed Sperling

Viewpoint—Ideas Under Test (1.6 pgs) (converting from EF format)

Software Development Principles Should be Applied to IC Design, By Simon Butler, CEO of Methodics

Editorial Feature—Synopsys (5 pages )done

“System Verilog, VMM Overcome WiMax Verification Challenges,” HeeDo Jung, Samsung Electronics, and Aditya Kher, Synopsys Inc.

tabs:

Editorial Feature--Mentor (3(-) pages) approved

> “SystemVerilog Comes of Age, by Mark Glasser, Mentor Graphics

Editorial Feature—CEVA (4(-) pages) approved

DSP-Core Evolution Powers Advancements in Communications and Multimedia Technologies, By Eran Briman, CEVA Inc.

Viewpoint—Ideas Under Test (1.6 pgs) (converting from EF format)

Software Development Principles Should be Applied to IC Design, By Simon Butler, CEO of Methodics

Editorial Feature—Forte (2.5 pages) done

High-Level Synthesis Improves Productivity without Sacrificing Area, Performance, or Power, ByBrett Cline and Mike Meredith, Forte Design Systems

Editorial Feature—LSI (3) still need copyright

> Design Specification Requirements with Verification in Mind, By Dave Fechser, LSI Corp.

DotOrg--Accellera(1.5 pages)approved.

“Accellera Technical Sub-Committee Enables VIP Interoperability and Reuse,” by Thomas Alsop, Intel Corp., co-chair of the VIP TSC

Viewpoint – No Respins, (1) (done)

Women in Technology: Crashing the Silicon Ceiling, By Holly Stump, VP Marketing, Jasper Design Automation

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Cover theme:DAC

Cover Heads:Smaller, Faster and More Parasitic