Chip Description Format

Chip description format, rev. 0.9

Introduction

This note describes chip description file format for Willem USB Programmer. It also provides information about all implemented programming algorithms, and gives several examples which should help user to add their own chips.

This note is organized as follows: Section 1 contains information about chip description file format in general. Sections 2 – 5 gives detailed information about each tag used in chip descriptions. Section 6 contains the list of implemented programming algorithms with notes about implementation and references to datasheets. Section 7 contains several examples of chip definitions with additional notes. And finally Section 8 describes differences in description of AVRs, PICs and serial EEPROMs in comparison with common memory descriptions.

Important note. Before working with newly added chip, it is strongly recommended to make sure that it uses correct programming algorithm and has THE SAME PINOUT; otherwise any action (even read operation) can damage data stored in this device.

1.Chip description file format

Chip description files are XML files by nature. Each file contains chip descriptions for one or more manufacturers. Each file has strictly defined hierarchy of tags shown below.

Each chip description file must have standard XML header <?xml … ?> at first line followed by one root tag <chips>…</chips>. All descriptions must be placed between opening tag <chips> and closing tag </chips>. Within <chips>…</chips> tag only one type of tags can be introduced. It is <manufacturer>…</manufacturer> tag type describing information about manufacturer (see Section 2 for details); one tag is introducedfor one manufacturer. Within <manufacturer>…</manufacturer> tag one or more <family>…</family> tags are placed. Each <family>…</family> tag specifies information about one family of chips (see Section 3 for details).Within <family>…</family> tag one or more <group> … </group> tags are placed. Each <group> … </group> tag specifies one group of chips, i.e. a set of chips having the same programming algorithm (see Section 4 for details). Within <group> … </group> tag one or more chip descriptions are placed. Each chip description is introduced by <chip>…</chip> tag (see Section 5 for details). Besides of chip descriptions group description contains other tags specifying programming algorithm, levels of Vcc & Vpp (if required), and other parameters.

Simplified structure of chip description file is represented below:

<?xmlversion="1.0" encoding="UTF-8"?>

chips

<manufacturer

<family> (start of family #1 description )

<group>

(group #1 description)

<chip>

(chip #1 in group #1 description)

</chip>

…

<chip>

(chip #N in group #1 description)

</chip>

</group>

<group>

(group #2 description)

</group>

…

<group>

(group #M description)

</group>

</family> (end of family #1 description)

(family #2 description)

</family>

…

(family #K description)

</family>

</manufacturer>

</chips>

All chip description files must be stored in chips subfolder of the User Interface folder.

2.Manufacturer description

Manufacturer description is contained in tag <manufacturer>. Completesyntaxfor this tag is shown below:

<manufacturer name = “[manufacturer name]”>

…

</manufacturer>

Parameters description:

Parameter / Type / Description
[manufacturername] / mandatory / Textstringcontainingmanufacturername. Thelistofmanufacturer’snamesconstitutes the first level of Chips menu in the User Interface.
Manufacturernamehastobeuniqueamong all other manufacturer names.

3.Familydescription

Chip family description is contained in tag <family>. Complete syntax for this tag is shown below:

…

</family>

Parameters description:

Parameter / Type / Description
[family name] / mandatory / Textstringcontainingchip familyname. Thelistoffamilynamesconstitutes the second level of Chips menu in the User Interface.
Chip family name has to be unique among all other family names for one manufacturer.

4.Group description

ChipgroupdescriptioncontainsinformationaboutgroupofchipswhichusethesameprogrammingalgorithmandthesameotherparameterslikeVccVpplevel, etc. Chip group description is contained in tag <group>. Complete syntax for this tag and all nested tags is shown below:

<algorithm>[algorithm name]</algorithm>

<gndbind>[ground pins]</gndbind>

<vccnorm>[normal vcc]</vccnorm>

<vccprogram>[program vcc]</vccprogram>

<vccerase>[erase vcc]</vccerase>

<vccverify>[verify vcc]</vccverify>

<vccdetect>[detect vcc]</vccdetect>

<vppnorm>[normal vpp]</vppnorm>

<vppprogram>[program vpp]</vppprogram>

<vpperase>[erase vpp]</vpperase>

<vppverify>[verify vpp]</vppverify>

<vppdetect>[detect vpp]</vppdetect>

<chipidlen>[chip id length]</chipidlen>

[chip descriptions]

</group>

Parametersdescription:

Parameter / Type / Description
[group name] / mandatory / Textstringcontaininggroup name.
Group name has to be unique among all other group names in one family.
[algorithm name] / mandatory / Text string. Programming algorithm name. It has to be one of names listed in the first column of table in section 6.
[ground pins] / mandatory / Text string. Number(s) of pin(s) which has to be connected to GND.
[vcc pins] / mandatory / Text string. Number(s) of pin(s) which has to be connected to Vcc.
[normal vcc] / optional* / Real number. Normal Vcc level in Volts.
This field allows to specify Vcc level for all operations (read/program/erase/verify/detect) using one tag. It’s useful in case then all or almost all operations require the same level of Vcc.
[read vcc] / optional* / Real number. Vcc level in Volts for read operation.
This tag has higher priority then <vccnorm> tag, i.e. if both tags <vccnorm> and <vccread> are specified in group description, Vcc level for read operation will be set up according to [read vcc] value.
[program vcc] / optional* / Real number. Vcc level in Volts for program operation.
[erase vcc] / optional* / Real number. Vcc level in Volts for erase operation.
[verify vcc] / optional* / Real number. Vcc level in Volts for verify operation.
[detect vcc] / optional* / Real number. Vcc level in Volts for chip identification (read chip id) operation.
[vpp pins] / optional / Text string. Number(s) of pin(s) which has to be connected to Vpp.
[normal vpp] / optional / Real number. Normal Vpp level in Volts.
This field allows to specify Vpp level for all operations using one tag.
[read vpp] / optional / Real number. Vcc level in Volts for read operation.
This tag has higher priority then <vppnorm> tag, i.e. if both tags <vppnorm> and <vppread> are specified in group description, Vcc level for read operation will be set up according to [read vpp] value.
[program vpp] / optional / Real number. Vpp level in Volts for program operation.
[erase vpp] / optional / Real number. Vpp level in Volts for erase operation.
[verify vpp] / optional / Real number. Vpp level in Volts for verify operation.
[detect vpp] / optional / Real number. Vpp level in Volts for chip identification operation.
[chip id length] / optional** / Integer number. Number of bytes in chip id sequence, i.e. number of bytes in manufacturer and device codes.See section5for additional information.
[chip descriptions] / mandatory / This part of group description contains information about each chip entering this group. See the next section for details.

Notes:

* At least one of [normal vcc] and operation specific [read/program/erase/verify/detect vcc] have to be specified for each operation implemented in programming algorithm. If operation specific tag is specified, it has higher priority then <vccnorm> tag.

** Chip detect operation will work correctly only if <chipidlen> tag is specified for the group and <chipid> tags are specified for each chip in the group.

5.Chip description

Chip description contains information about one chip: chip name, chip size, and chip identification code. This information is contained in tag <chip> … </chip>and in nested tags. Complete syntax for this tag is shown below:

chipname = “[chipname]”>

</chip>

Parametersdescription:

Parameter / Type / Description
[chip name] / mandatory / Textstringcontainingchip name. Thelistofchipnamesconstitutes the third level of Chips menu in the User Interface.
Chip name has to be unique among all other chip names in one group.
[chip size] / mandatory / Integernumber. Chipsizeinbits.
[chip id] / optional / This field specifies manufacturer and device codes.
Hexadecimal number, bytes have to be delimited by spaces. Number of bytes required is specified by <chipidlen>tag in group description.
It may contain don’t care bytes specified as “xx”.

6.Programming algorithms

Thissectioncontainscompletelistofimplemented algorithms for memory chips.For each algorithm reference chip and package is shown, and link to datasheet for that chip is presented. Table also shows implementation-specific parameters and notes about operation modes and delays for each algorithm.

This table doesn’t contain any information about algorithms for AVRs, PICs, and serial EEPROMs. This information can be found in TBD.

Name / OPS, AW, DW* / Notes
28CD24P00 / OPS: R, P, E
AW: 19
DW: 8 / Reference chip: ATMEL AT28C16
Reference package: DIP24
Read: 0.45 us access time
Program: byte-by-byte with data pooling
Erase: one 10 ms erase pulse
Reference chip URL:
28CD24P16 / OPS: R, P, E
AW: 19
DW: 8 / Reference chip: XICOR X2816C
Reference package: DIP24
Read: 0.45 us access time
Program: page-by-page with data pooling, page size: 16
Erase: one 10 ms erase pulse
Reference chip URL:
28CD28P00 / OPS: R, P, E
AW: 19
DW: 8 / Reference chip: ATMEL AT28BV64
Reference package: DIP28
Read: 0.45 us access time
Program: byte-by-byte with data pooling
Erase: one 10 ms erase pulse
Reference chip URL:
28CD28P32 / OPS: R, P, E
AW: 19
DW: 8 / Reference chip: XICOR X2816C
Reference package: DIP28
Read: 0.45 us access time
Program: page-by-page with data pooling, page size: 32
Erase: one 10 ms erase pulse
Reference chip URL:
28CD32P128 / OPS: R, P, E
AW: 19
DW: 8 / Reference chip: ATMEL AT28C040
Reference package: DIP32
Read: 0.45 us access time
Program: page-by-page with data pooling, page size: 128
Erase: one 10 ms erase pulse
Reference chip URL:
28CL32P00 / OPS: R, P, E
AW: 19
DW: 8 / Reference chip: ATMEL AT28BV64
Reference package: PLCC32
Read: 0.45 us access time
Program: byte-by-byte with data pooling
Erase: one 10 ms erase pulse
Reference chip URL:
28CL32P16 / OPS: R, P, E
AW: 19
DW: 8 / Reference chip: XICOR X28C513
Reference package: PLCC32
Read: 0.45 us access time
Program: page-by-page with data pooling, page size: 16
Erase: one 10 ms erase pulse
Reference chip URL:
AM29F / OPS: R, P, E, I
AW: 19
DW: 8 / Reference chip: AMD AM29F040B
Reference package: DIP32
Mode: SDP** on
Read: 0.45 us access time
Program: byte-by-byte with data pooling
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
AM29F002 / OPS: R, P, E, I
AW: 19
DW: 8 / Reference chip: AMD AM29F002
Reference package: DIP32
Mode: SDP on
Read: 0.45 us access time
Program: byte-by-byte with data pooling
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
AM29LV / OPS: R, P, E, I
AW: 22
DW: 16 / Reference chip: AMD AM29LV640MB
Reference package: TSOP48
Mode: Word configuration
Read: 0.50 us access time
Program: byte-by-byte with data pooling
Erase: data pooling
Chip identification sequence length: 4
Reference chip URL:
AT29C020 / OPS: R, P, E, I
AW: 19
DW: 8 / Reference chip: ATMEL AT29C040A
Reference package: DIP32
Mode: SDP on
Read: 0.45 us access time
Program: page-by-page with data pooling, page size: 256
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
AT29C256 / OPS: R, P, E, I
AW: 15
DW: 8 / Reference chip: ATMEL AT29C256
Reference package: PLCC32
Mode: SDP on
Read: 0.45 us access time
Program: page-by-page with data pooling, page size: 64
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
AT29C256D28 / OPS: R, P, E, I
AW: 15
DW: 8 / Reference chip: ATMEL AT29C256
Reference package: DIP28
Mode: SDP on
Read: 0.45 us access time
Program: page-by-page with data pooling, page size: 64
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL: not found
AT29C512 / OPS: R, P, E, I
AW: 19
DW: 8 / Reference chip: ATMEL AT29C010A
Reference package: PLCC32
Mode: SDP on
Read: 0.45 us access time
Program: page-by-page with data pooling, page size: 128
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
I28F001 / OPS: R, P, E, I
AW: 17
DW: 8 / Reference chip: INTEL 28F001BX
Reference package: DIP32
Read: 0.50 us access time
Program: byte-by-byte, EOP detection from status register
Erase: EOP detection from status register
Chip identification sequence length: 2
Reference chip URL:
I28F0x0 / OPS: R, P, E, I
AW: 18
DW: 8 / Reference chip: INTEL P28F010
Reference package: DIP32
Read: 0.50 us access time
Program: page-by-page, page size: 256, end of operation detection is similar to data pooling
Erase: end of operation detection is similar to data pooling
Chip identification sequence length: 2
Reference chip URL:
I28Fx16 / OPS: R, P, E, I
AW: 22
DW: 16 / Reference chip: INTEL TE28F320B3B
Reference package: TSOP48
Read: 0.50 us access time
Program: byte-by-byte with data pooling
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
M2716 / OPS: R, P
AW: 12
DW: 8 / Reference chip: ST M2716
Reference package: DIP24
Read: 0.90 us access time
Program: byte-by-byte, one 50 ms program pulse
Reference chip URL:
M2716F / OPS: R, P
AW: 12
DW: 8 / It is faster then M2716 algorithm, but it is not standard, programming is done according to the algorithm for AM27C512
Reference chip: ST M2716
Reference package: DIP24
Read: 0.90 us access time
Program: byte-by-byte, series of 100 us pulses, up to 25 pulses for each address
Reference chip URL:

M27C040 / OPS: R, P
AW: 19
DW: 8 / Reference chip: ATMEL AT27C040
Reference package: DIP32
Read: 0.90 us access time
Program: byte-by-byte, series of 100 us pulses, up to 25 pulses for each address
Reference chip URL:
M27C080 / OPS: R, P
AW: 20
DW: 8 / Reference chip: ATMEL AT27C080
Reference package: DIP32
Read: 0.90 us access time
Program: byte-by-byte, series of 100 us pulses, up to 25 pulses for each address
Reference chip URL:
M27C4096 / OPS: R, P
AW: 18
DW: 16 / Reference chip: AMD AM27C4096
Reference package: DIP40
Read: 0.90 us access time
Program: byte-by-byte, series of 100 us pulses, up to 25 pulses for each address
Reference chip URL:
M27CP28LX8 / OPS: R, P
AW: 14
DW: 8 / Reference chip: INTEL 27C128
Reference package: DIP32
Read: 0.90 us access time
Program: byte-by-byte, series of 100 us pulses, up to 25 pulses for each address
Reference chip URL:
M27CP28X8 / OPS: R, P
AW: 17
DW: 8 / Reference chip: AMD AM27C512
Reference package: DIP32
Read: 0.90 us access time
Program: byte-by-byte, series of 100 us pulses, up to 25 pulses for each address
Reference chip URL:
M27CP32X8 / OPS: R, P
AW: 18
DW: 8 / Reference chip: AMD AM27C020
Reference package: DIP32
Read: 0.90 us access time
Program: byte-by-byte, series of 100 us pulses, up to 25 pulses for each address
Reference chip URL:
M27CP40X16 / OPS: R, P
AW: 17
DW: 16 / Reference chip: AMD AM27C2048
Reference package: DIP40
Read: 0.90 us access time
Program: byte-by-byte, series of 100 us pulses, up to 25 pulses for each address
Reference chip URL:
M27P24X8 / OPS: R, P
AW: 12
DW: 8 / Reference chip: ST M2732
Reference package: DIP24
Read: 0.90 us access time
Program: byte-by-byte, one 50 ms program pulse
Reference chip URL:
M27P24X8F / OPS: R, P
AW: 12
DW: 8 / It is faster then M27P24X8 algorithm, but it is not standard, programming is done according to the algorithm for AM27C512
Reference chip: ST M2732
Reference package: DIP24
Read: 0.90 us access time
Program: byte-by-byte, series of 100 us pulses, up to 25 pulses for each address
Reference chip URL:

MX28Fx000 / OPS: R, P, E, I
AW: 18
DW: 8 / Reference chip: MXIC MX28F2000P
Reference package: DIP32
Read: 0.50 us access time
Program: byte-by-byte with data pooling
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
SST29EE / OPS: R, P, E, I
AW: 19
DW: 8 / Reference chip: SST 29EE020
Reference package: DIP32
Mode: SDP on
Read: 0.50 us access time
Program: page-by-page with data pooling, page size: 128
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
SST39SF / OPS: R, P, E, I
AW: 19
DW: 8 / Reference chip: SST 39SF040
Reference package: DIP32
Mode: SDP on
Read: 0.12 us access time
Program: byte-by-byte with data pooling
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
SST49LF / OPS: R, P, E, I
AW: 19
DW: 8 / Reference chip: SST 49LF008A
Reference package: PLCC32
Mode: PP Mode, SDP on
Read: 0.12 us access time
Program: byte-by-byte with data pooling
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
W29EE128 / OPS: R, P, E, I
AW: 19
DW: 8 / Reference chip: Winbond W29C020
Reference package: DIP32
Mode: SDP on
Read: 0.50 us access time
Program: page-by-page with data pooling, page size: 128
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:
W29EE256 / OPS: R, P, E, I
AW: 19
DW: 8 / Reference chip: Winbond W29C040
Reference package: DIP32
Mode: SDP on
Read: 0.50 us access time
Program: page-by-page with data pooling, page size: 256
Erase: data pooling
Chip identification sequence length: 2
Reference chip URL:

Notes:

* OPSspecifies list of operations implemented for the given algorithm (“R” – read/verify, “P” – program, “E” – erase, and “I” – chip detect, chip id read); AW is address bus width; DW is data bus width.

** SDP = Software Data Protection

7.Chip description examples

This section contains several chip description examples which should help user to add their own chips to the User Interface.

Example 1. This example shows descriptions for four chips (SST29SF512, SST29SF010, SST29SF020, and SST29SF040) manufactured by SST belonging to one family (SST29SF) and having the same programming algorithm (SST39SF algorithm with 5V Vcc connected to pin#48 and GND connected to pin #16). These chips are joined in one group because they use absolutely the same programming algorithm, have identical pinout, and require the same level of Vcc. These chips have chip identification feature, that’s why <chipidlen> and <chipid> tags are presented in description. All operations (read/program/erase/verify/detect) require the same level of Vcc, therefore <vccnorm> tag is used to specify Vcc level instead of <vccread>, <vccprogram>, <vccerase>, <vccverify>, and <vccdetect> tags.

<?xml version="1.0" encoding="UTF-8"?>

<chips>

</chip>

</chip>