Department Ofelectronics &Instrumentationengineering

Department ofElectronics &InstrumentationEngineering

Year/Sem :II/IV

Sub/ Code : DigitalLogic Circuits

PART A

UNITI-NUMBER SYSTEMSBOOLEANALGEBRA

1. Convert thehexadecimalnumberE3FA to binary. (EINov 2007)

Solution:

E3FA16– Hexadecimal

E 3 F A

11102 00112 11112 10102

So the equivalent binaryvalue is 11100011111110102

2. Perform the followingconversion (1029)10to gray (EE May2006)

Solution:

1 / 0 / 2 / 9 / ----- Decimal
0001 / 0000 / 0010 / 1001 / ----- BCD
0001 / 0000 / 0011 / 1101 / ----- Gray

Thus the Graycodeof 102910is 00010000001111012

3. Add 1A816and 67B16 (EE Nov 2004)

Solution:

1 A 816

6 7 B16

------

8 2 316

------

=82316

4. Show theKarnaugh mapwith the encircledgroupsforthe Boolean function,

F =C’+A’D’+A’B’D’. (EE May2006)

Solution:

1 / 1 / 1
1 / 1 / 1
1 / 1
1 / 1 / 1

5. Perform 2s complementsubtraction of010110-100101. (Nov 2004)

Solution:

1’s complement ofminuend100101 =011010

2’s complement of011010 =011011

Addition of010110 +011011 = 110001

Thereis no endcarry.

Therefore, theanswer is–(2’s complement of110001)

Answer =-001111

6. ApplyDemorgan’s theorems to simplify(A+BC')'. (Apr 2004)

Solution:

(A+BC')'=A'.(BC')'

=A'. (B'+C)

7. Plot the expression on K-Map F(w, x,y)=Σ(0,1,3,5,6)+d(2,4). (Apr 2004)

Solution:

W XY

1 / 1 / 1 / X
X / 1 / 1

F=x'+xy'+w’

8. IfA andBare Boolean variables and ifA=1 and(A+B)'=0, findB. (Nov 2003)

Solution:

IfB=0 (A+B)’=0

If B=1 (A+B)’=0

Hencethevalue ofB=0 (or) 1 i.eDon’t care

12.If A andBare Boolean variablescheck if (A.A')(A A')=(B+B') (B'B).

(Apr 2003)

A / A’ / AA’ / AA’ / (AA’)(AA’) / B / B’ / B+B’ / B’B / (B+B’) (B’B)
0 / 1 / 0 / 1 / 1 / 0 / 1 / 1 / 1 / 0
1 / 0 / 0 / 1 / 1 / 1 / 0 / 1 / 1 / 0

L.H.S #R.H.S (Not equal)

14. What is the featureofgraycode? What areits applications (EC Nov 2007/May2006)

Solution:

Theadvantageofgraycodealsocalledreflectedcodeoverpurebinarynumbersis thatanumberingraycodechangesbyonlyonebitasitproceedsfromonenumbertothe next.Atypicalapplicationofthereflectedcodeoccurswhentheanalog dataare represented byacontinuouschangeofashaftposition.Theshaftisportionedintosegmentsandeach

segmentis assignedanumber. Ifadjacentsegmentaremadetocorrespondtoadjacent reflected-code numbers, ambiguityis reduced when detection is sensed in the line that separates anytwo segments.

Soin3-bitcode,errormay occurduetoonebitposition,othertwobitpositionsof adjacent sectorsare alwayssame and hencethereis no possibilityoferror.Thus in 3-bitcode, probabilityoferror is reduced to 66 % and in 4-bitcodeitis reduced upto 25%.

15. Convert thegraycodenumber11011 to binary. (Nov 2006)

Solution:

graycode

binarycode=10010

16. What is even parity? (Nov 2006)

Solution:

Aparity bitisanextrabitincludedwithamessagetomakethetotalnumberof1’s either odd or even. If the total number of 1’s is even then it is called even parity.

17. Find the2’s complementand 1’s complement of101101. (EC May2006)

Solution:

1’s complement of101101 =010010

2’s complement of101101 =010010

------

010011

------

18. SimplifyX1+X1 X2. (EC May2006)

Solution:

x1 +x1x2

=x1(1+x2)

=x1

19. Find thestandard sum for thefollowing function. (EC May2006)

f =x1 x2x3 +x1x3x4+x1x2x4.

Solution:

f =x1 x2x3 +x1x3x4+x1x2x4

=x1x2x3(x4+x4’)+x1(x2+x2’)x3x4+x1x2(x3+x3’)x4

=x1x2x3x4 +x1x2x3x4’+x1x2’x3x4 +x1x2x3’x4

(Hint:standard sum means canonical POS)

20. Convert binarynumber11011110 into its decimal equivalent. (May2007)

Solution:

1 1 0 1 1 1 1 0

------0 * 20=0

------1 * 21=2

------1 * 22=4

------1 * 23=8

------1 * 24=16

------0 * 25=0

------1 * 26=64

------1 * 27=128

------

222

23. Convert thebinarynumber 1011 tograycode. (May2007)

Solution:

Graycodeof 1011 is 1110

24. Minimisethe function usingBoolean algebra f =x(y+w’z)+wxz. (May2007)

Solution:

F=x(y+w’z)+wxz

=xy+xw’z+wxz

=xy+xz(w’ +w)

=xy+xz

25. Determinethe decimal numberrepresented by101101.10101. (May2008)

Solution:

101101.10101

------1*2-5=0.03125

------0*2-4=0

------1*2-3=0.125

------0* 2-2=0

------1* 2-1=0.5

------1*2 0 =1

------0*21 =0

------1*22 =4

------1*23=8

------0*24 =0

------1*25=32

------

45.65625

------

26. Convert (0.513)10to octal. (Nov 2007)

Solution:

0.513 * 8 =4.104 4

0.104 * 8 =0.832 0

0.832 *8 =6.565 6

0.656 *8 =5.248 5

0.248 *8 =1.984 1

0.984 *8 =7.872 7

(0.513)10 =( 0.406517..)8

27. Express F=A+B’C as sum of minterms. (Nov 2007)

Solution:

F=A+B’C

Thefunction has threevariables A,B, C . Thefirstterm A is missingtwo variablesB

and C.Thesecond term is missingonevariableso

F=A(B+B’) (C+C’) +(A+A’)B’C

=ABC+ABC’+AB’C’+AB’C+A’B’C+AB’C

=ABC+ABC’+AB’C’+AB’C+A’B’C since(x+x=x)

=m7 +m6+m4 + m5+m1 (arrangein ascendingorder)

=m1+m4+m5+m6+m7

28. Using2’scomplement perform thegiven subtraction (1001101)2– (110100)2

Solution:

Take2’s complement for0110100--1001011 (Nov 2007)

+ 1

------

1001100

------

1001101

+1001100

------

10011001 discard theend carryans is001100

29. Provethat A+A'B=A+B, Using Boolean algebra. (Nov 2005) Solution:

A+A’B=(A+A')(A+B)

=1 (A+B) whereA+A' =1

=A+B

30. Construct thetruth table of F=(AB)(CD).

Solution:

S.No / A / B / C / D / AB / CD / F=(AB)(CD)
1 / 0 / 0 / 0 / 0 / 0 / 0 / 0
2 / 0 / 0 / 0 / 1 / 0 / 1 / 1
3 / 0 / 0 / 1 / 0 / 0 / 1 / 1
4 / 0 / 0 / 1 / 1 / 0 / 0 / 0
5 / 0 / 1 / 0 / 0 / 1 / 0 / 1
6 / 0 / 1 / 0 / 1 / 1 / 1 / 0
7 / 0 / 1 / 1 / 0 / 1 / 1 / 0
8 / 0 / 1 / 1 / 1 / 1 / 0 / 1
9 / 1 / 0 / 0 / 0 / 1 / 0 / 1
10 / 1 / 0 / 0 / 1 / 1 / 1 / 0
11 / 1 / 0 / 1 / 0 / 1 / 1 / 0
12 / 1 / 0 / 1 / 1 / 1 / 0 / 1
13 / 1 / 1 / 0 / 0 / 0 / 0 / 0
14 / 1 / 1 / 0 / 1 / 0 / 1 / 1
15 / 1 / 1 / 1 / 0 / 0 / 1 / 1
16 / 1 / 1 / 1 / 1 / 0 / 0 / 0

31. Writethe De-morgans theorem. (EINov 2007, Nov 2006,Apr2005, EIMay’10)

Solution:

(A+B)'= A'.B' (A.B)'=A' +B'

Demorganslawsaremostlyusefulinsimplifyingexpressionsinwhichproductsorsum variables areinverted.

32. SimplifyXY’+ZXY’ (EIApril2011)

=XY’(1+Z)

=XY’

33. Simplifythefunction Y=Σ (1,3,5,7)W XY (EIMay/June2013)

Y=Y

34 .What is hammingcode? (EIDEC 2013)

Oneofthemostcommonmethodoferrorcorrecting.Itconsistofkparitybitsthatareadded to n-bitdata word forminganew n+k bits

35 .What areredundant primeimplicants? (EIDEC2013)

Theprimeimplicantwhoseeachone1iscovered by atleastoneessentialprimeimplicantsis called redundant primeimplicants.

UNITII-COMBINATIONAL CIRCUITS

1. Writethe procedural steps forthe designofcombinational circuits.(EI May 2009). Solution:The designofcombinationalcircuitstartsfroma specificationof the problem culminatesinalogicdiagramorsetofBooleanequationsfromwhichthelogicdiagramcan beobtained.

Theprocedureinvolves thefollowingsteps:

1. From the specifications of the circuit, determinethe required numberofinputs and outputs, and assign aletter symbolto each.

2. Derivethe truth tablethat defines the requiredrelation ship between inputs and outputs.

3. Obtain thesimplified Booleanfunctions of each outputas function ofthe input variables.

4. Draw thelogic diagram.

5. Verifythecorrectnessof thedesign.

2. Give thetruth tablefor4 bit priority encoder. (EI May 2009)

Solution:

A4-bitpriorityencoder(alsosometimescalledaprioritydecoder).Thiscircuitbasically convertsthe4-bitinputintoabinaryrepresentation.Iftheinputnisactive,alllowerinputs (n-1…0)areignored:

X3 / X2 / X1 / X0 / Y1 / Y0
1 / X / X / X / 1 / 1
0 / 1 / X / X / 1 / 0
0 / 0 / 1 / X / 0 / 0
0 / 0 / 0 / X / 0 / 0

Thecircuitoperationissimple.Eachoutputisdrivenby anOR-gatewhichis connectedtothe NAND-INVoutputsofthecorresponding inputlines. TheNANDgateof each stages receivesitsinputbit, aswellastheNANDgate outputsofallhigher priority stages.Thisstructureimpliesthatanactiveinputonstageneffectively disablesalllower stages n-1.. 0.

Notethat the circuitfunction as specified heredoes not depend at all on theleast significant inputbit.

Acommonuseofpriorityencodersisforinterruptcontrollers,toselectthemostcriticalout of multipleinterruptrequests.Due toelectricalreasons(opencollectoroutputs),priority encoderswith active-lowinputs arealso often used in practice.

3. Drawthe Truth Table ofFullAdder. (EI Nov 2007) Solution:

Input / Output
C / B / A / Sum / Carry
0 / 0 / 0 / 0 / 0
0 / 0 / 1 / 1 / 0
0 / 1 / 0 / 1 / 0
0 / 1 / 1 / 0 / 1
1 / 0 / 0 / 1 / 0
1 / 0 / 1 / 0 / 1
1 / 1 / 0 / 0 / 1
1 / 1 / 1 / 1 / 1

Truth Table

4. Realizef= A'B + AB' using minimumuniversalgates. (Nov 2005) Solution:

f=A'B+AB'=

A’

B’

5. Drawa tristateinverterand drawits truth table (Nov2005). Solution:

A tri-statebuffer is auseful devicethat allows usto control when current passes through the device, andwhen itdoesn't. Here aretwo diagrams of thetri-statebuffer.

Here'satruth table describingthe behavior ofan active-high tri-statebuffer.

C / X / Z
0 / 0 / Z
0 / 1 / Z
1 / 0 / 0
1 / 1 / 1

6. Drawa combinational logic circuit which cancomparewhethertwobit binary numbers aresameornot.

Solution:

(Nov 2005)

Which is similarto EX-NOR operation Y=A’B’+AB

7. What is combinational circuit? Give an example. (Apr2005) Solution:

A combinational circuit consists of logic gates whose outputs at any time are

determinedfromthepresentcombinationofinputs.Examplesofcombinationalcircuitsare adder, coder, magnitudecomparatoretc.

8. What arethe universal gates? (Nov 2004) Solution:

NANDandNORareuniversalgates,becausetheyreplacealltheothergatesina

circuit.

9. Obtain 3 level NOR– NOR implementationof f(a,b,c,d,e,f)=[ab+cd ]ef. (Nov 2004)

f (a, b, c, d,e, f)=[ab+cd ]ef

Solution:

= abef+cdef

F’= (abef + cdef)’

=(abef)’.(cdef)’

= a+b+e+f . c+d+e+f

10. Drawa 1 to 2-demultiplexer circuit. (Nov 2003) Solution:

11. Drawa 2 to 1 multiplexer circuit. (Nov 2003) Solution:

12. What is demux? (EC Nov 2007/Apr2004)

Solution:

Demultiplexerisacircuitthatreceivesinformationonasinglelineandtransmitsthis

informationononeof2npossibleoutputlines.Ademultiplexerisadecoderwithanenable input.

13. Drawa parity checker circuit for3 bit binary wordx1 x2 x3. (May 2006) Solution:

14. What does LSin74LS00 indicate? (Nov 2006) Solution:

Low power schottkyTTL

15. Definepriority encoder. (Nov 2006) Solution:

Encoders establish an inputpriorityto ensurethatonlythe highest-priorityinputline

is encoded.Ifpriorityisgiven to an inputwithhigher subscript number over onewith lower subscriptnumber, then ifboth D2 and D5 arelogic-1 simultaneously, the outputwillbe101 becauseD5 has ahigherpriorityover D2.

Inputs
D0 D1 D2 D3 D4 D5 D6 D7 / Outputs
X yz
1 0 0 0 0 0 0 0
X 1 0 0 0 0 0 0
X X 1 0 0 0 0 0
X X X 1 0 0 0 0
X X X X 1 0 0 0
X X X X X 1 0 0
X X X X X X 1 0
X X X X X X X 1 / 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

16.RealizeS(X,Y,Z)=∑(1,2,3,4)usinganappropriatedecoderandanexternallogic

gates. (Nov 2006)

Solution:

A Y0

B Y1

C Y2

3:8 Y4

EN’

17. Represent a halfadderin block diagramformandalso its logicimplementation. (EC May2006\May2007)

Solution:

A C

B S

Inputs / Y =A+B
A / B / carry / Sum
0 / 0 / 0 / 0
0 / 1 / 0 / 1
1 / 0 / 0 / 1
1 / 1 / 1 / 0

Carry

B A

Sum

Carry=AB

B A

Sum=A’B+AB’

18. What arethemajor categories oflogic circuits? (May 2007)

Solution:

Themajorcategoriesoflogiccircuitsarecombinationallogiccircuitandsequential

logic circuit.

19. Designa 2 input NANDgateusing 2: 1multiplexer. (May 2007) Solution:

A / B / Y
0
0
1
1 / 0
1
0
1 / 1
0
0
0

Io I1

A’ 0 1

A 2 3

A’ 0

A’

0 V I1

2X1

20.FindtherelationbetweentheI/PsandO/P,showninfigure.Nametheoperation

performed. (May 2008)

Solution:

A Y

Y =A’.B’=( A+B)’

This gate performs the NOR operation.

S0S1 / Output
00
01
10
11 / I0
I1
I2
I3

21. Writethetruth tableofa 4:1multiplexer.(May 2008) Solution:

22. Drawthe logicdiagramfor X=AB +B’C.(Nov 2007)

Solution:

B’

23. ImplementF= (AB’+ A’B)(C+D’)with only NORgate.(Nov 2007)

F=(AB’ +A’B)(C+D’)

Solution:

F=AB’C +A’BC +AB’D’+A’BD’

F’ = (AB’C +A’BC +AB’D’+A’BD’)’

=(AB’C)’(A’BC)’(AB’D’)’(A’BD’)’

F‘ = (A’+B+C’)(A+B’+C’)(A’+B+D)(A+B’+D)

24. Implement thefunction f= ∑m(0,1,4,5,7) using8:1 MUX. (Nov2007)

Solution:

+5V

3 8X1

output

25. Specify the use ofMultiplexers (EI Nov 2007) Solution:

The applications of Multiplexers are

1. Data Selection

2. Data Routing

3. operation Sequencing

4. Parallel to serial conversion

5. Waveform Generation

6. Logicfunctiongeneration

26. Designa HalfSubtractor. (EI April’10)

Solution:

X / Y / D / B
0 / 0 / 0 / 0
0 / 1 / 1 / 1
1 / 0 / 1 / 0
1 / 1 / 0 / 0

D=XY’+X’Y=Xxor Y

B=X’Y

Inputs / Y =A+B
A / B / carry / Sum
0 / 0 / 0 / 0
0 / 1 / 0 / 1
1 / 0 / 0 / 1
1 / 1 / 1 / 0

28Writethetruthtableforhalfadder?(EIMay/June’13)

29. .Howthe decoder isused as demultiplexer?(EI Nov/Dec’13)

Theselection lines of theDEMUXcan beusedas inputlines ofdecoderand ifthe data inputofthe demultiplexeris used as the enable inputofthe decoder then we can usethe demultiplexer as adecoder.

UNITIII-SYNCHRONOUS SEQUENTIAL CIRCUITS

1. What areshift registercounters? List two widely usedshift register counters. (EE Dec2004).

Solution:

Iftheoutputofashiftregisterisfedbacktotheinput.aringcounterresults.Thedata pattern containedwithin theshift register willrecirculate as long as clock pulses areapplied.

2. Why is FlipFlopalso knownasLatch? (EC Nov 2007) Solution:

Thedifferencebetweenalatchandaflip-flopisthatalatchdoesnothaveaclocksignal,

whereasaflip-flopalwaysdoes.Latchisalevelsensitivedevice while flip-flopisanedge sensitive device.Latch issensitive toglitchesonenable pin,whereasflip-flop isimmune to that.

3. Compare Mooreand Mealy Machine. (EC Nov 2007)

Sl.No / MooreModel / MealyModel
1. / Itsoutputisafunctionofpresentstate
only. / Itsoutputisafunctionofpresentstate
as wellas present input
2. / Input changes does not affect the
output / Inputchangesmayaffecttheoutputof
the circuit
3. Itrequiresmorenumberofstatesfor
implementingthefunction / It require less number of states for implementing the function

4. Obtain the excitationtableof D-FlipFlop (EE May 2006)

Q / Q(t+1) / D
0
0
1
1 / 0
1
0
1 / 0
1
0
1

5. What arestatediagramandstatetables? (EE May 2006)

Solution:

Thetimesequenceofinputs,outputsandflip-flopstatesmay beenumeratedinastate tableandtheinformationavailableinastatetablemay berepresentedgraphicallycalleda statediagram.Forthedesignofsequentialcounterswe havetorelatepresentstatesandnext states. Thetable,whichrepresents therelationship between present states and next states, is called state table.

6. Give theexcitationtableforJK FlipFlop (EI Nov 2007) Solution:

Q / Q(t+1) / J / K
0
0
1
1 / 0
1
0
1 / 0
1
X X / X
X
1
0

7. Drawthe logicdiagramforTFlipFlop (EI Nov 2007) Solution:

8. Howmany flip-flopsarerequiredto designa mod-7 up-downcounter?(Nov2005) Solution:

Flip Flops required are

2n =N where N=7

2n =7 n =Numberof FlipFlops. n =3 Hence3Flip Flops arerequired

9. What is a sequentialcircuit? (Apr2005) Solution:

Thelogiccircuitswhoseoutputsatany instantoftimedependnotonly onthepresent inputs but also on the past outputs are called sequential circuits. Example: flip-flops.

10. Drawthe logicdiagramof SR flip-flop. (Apr2005) Solution:

11. Derive TFFfromJK FF. (EC May 2007) Solution:

Excitation tablefor above conversion

Input / Present state / Next state / Flip-flop inputs
T / Qn / Qn+1 / J / K
0
0
1
1 / 0
1
0
1 / 0
1
1
0 / 0
X
1
X / X
0
X
1

J =T

K =T

12. Drawthe timing diagramof4-bit ring counter. (Nov 2004)

13. Writethecharacteristic equation ofJKflip-flop. (Apr2004) Solution:

Q(t + 1)=JQ'+K'Q

14. Convert SRFlip flopto Dflipflop. (EI Apr’10,Apr 2004)

Solution:

Input / Present state / Next state / Flip-flop inputs
D / Qn / Qn+1 / S / R
0
0
1
1 / 0
1
0
1 / 0
0
1
1 / 0
0
1
X / X
1
0
0

Excitation tablefor above conversion

15. Statea limitationof SR flip-flop. (Nov 2003)

Solution:

ThelastinputconditioninSRflip-flopisS=1andR=1.ThisConditionwillproduce

0attheoutputofboththeNORgate.HenceQn+1=0andQ'n+1=0.Thisconditionviolatesthe factthattheoutputsQn+1andQ'n+1arethecomplementsofeachother.Innormaloperation, this condition must beavoided bymaking

surethat 1s arenot a applied to both inputs simultaneously.

16. Convert a Dflip-flopinto Tflip-flop. (Nov 2003) Solution:

Excitation tablefor above conversion

Input / Present state / Next state / Flip-flop inputs
T / Qn / Qn+1 / D
0 / 0 / 0 / 0
0
1
1 / 1
0
1 / 1
1
0 / 1
1
0

D =TQ’+T’Q =TQ

17. Ifa serial–inserial–out shift registerhas N stages andifthe clock frequency is f, whatwillbethe timedelay betweeninput andoutput? (Nov 2003)

Solution:

Thetime delaybetween inputband outputis TD=f

18. What is the conditionofa JKflip-flopto workas a D flip-flop? (Apr2003) Solution:

J=D and K=D’

19. What is the race- aroundcondition? (Apr2003) Solution:

InJKFFoutputisfedbacktotheinputandthereforechangeintheoutputresultsin

changein theinput.If theFFis level trigged, in thepositivehalf ofthe clock pulseif

jandkarebothhighthenoutputtogglescontinuously.Thisconditionisknownasrace around condition.

20. What is a flip–flop? (EC May 2006) Solution:

Aflip-flopcircuitcanmaintainabinarystateindefinitelyuntildirectedbyaninput

signaltoswitchstates.Themajordifferencesamongvarioustypesofflip-flopsareinthe numberof inputs theypossess and in themanner in which the input affect thebinarystate.

21. Differentiatebetweenedge-triggered flip-flopandlevel triggered flip-flop.

(ECMay2006)

Solution:

Anedgetriggeredflipflopchangesstateeitheratthepositiveedge(risingedge)orat thenegativeedge(fallingedge)oftheclockpulseandissensitivetoitsinputsonly atthis transition of the clock pulse.

22. What arethe nextstate equations ofRS andJK FFs? (Nov 2006)

(characteristic equations arealso called asnext state equations)

Solution:

Q(t+1)=JQ’+K’Q Q(t+1)=S+R’Q

23. Howdoes a J-Kflip-flopdiffer fromanS-R flipflopinitsbasic operation?

(Nov 2006/ May2007)

Solution:

A JK flip-flop is a refinement oftheRSflip-flop in that the indeterminate state ofthe RSisdefinedinthe JKtype.InputsJandKbehavelikeinputsSandRtosetandclearthe flip-flop.Wheninputsare appliedtobothJandKsimultaneously,theflip-flopswitchestoits complement state, that is ,if Q =1 itswitches to Q=0 and vice-versa.

24. Definesynchronouscounter. (Nov 2006) Solution:

Acounterisaregistercapableofcountingthenumberofclockpulsesarrivingatits

clockinput.Countrepresentsthenumber ofclockpulses arrived.Twotypesofcounter synchronousandasynchronous .Insynchronouscounterthecommonclockinputis connected to all of theflip-flop andthus theyareclocked simultaneously.

25. Classify the registerwith respect to serialand parallel input output. (May 2007) Solution:

Theshift registercanbe classified in to (i)Serial in serial out (ii) Serial in parallel out

(iii)parallel in serial out (iv) Parallel in parallel out

26.WritethecharacteristicsequationofJKFFandshowhowJKFFcanbeconverted into T FF? (May 2007)

Solution:

Q(t + 1)=JQ'+K'Q

Input / Present state / Next state / Flip-flop inputs
T / Qn / Qn+1 / Ja / Ka
0
0
1
1 / 0
1
0
1 / 0
1
1
0 / 0
X
1
X / X
0
X
1

27. Drawthe logicsymbolandtruth tableofaD flipflop. (May 2008)

Solution:

Q / D / Q(t+1)
0
0
1
1 / 0
1
0
1 / 0
1
0
1

30. What is Mooremachine? (Nov 2007) Solution:

Its outputdepends onlyon the present state of theflip flop.

Input changes does not affect theoutput

It requires morenumberof statesforimplementingsamefunction

UNITIV-ASYNCHRONOUS SEQUENTIALCIRCUITS

1. What is thedifferencebetweensynchronousandasynchronous circuit?(EI Nov07). Solution:

Synchronous Circuit / Asynchronous circuit
Synchronoussequentialcircuitisasystem
whosebehavior can be defined from the knowledge of the signals at discrete instants of time. / Thecircuitinwhichthechangeintheinput
signalscanaffectmemory elementsatany instantsofthe timeiscalledAsynchronous circuit.
The signals can affect the memory
elements onlyat discreteinstants of time. / Inthiscircuit,clockisabsentandhencethe
statechangescanoccuraccordingtodelay time ofthe logic.
Easierto design / Moredifficult to design
Memoryelements areclocked FlipFlops / Memory elements are either unclocked
flipflops or timedelayelements.

2. What arethe different modes ofoperation inasynchronous sequentialcircuits?

(ECMay2007)

Solution:

Thedifferent modes of operation arefundamentalmode and sequential mode circuits.

3. Why areasynchronous counters referredto asripple counters?(EI May 2007) Solution:

CountercircuitsmadefromcascadedJ-Kflip-flopswhereeachclockinputreceives itspulsesfromtheoutputofthepreviousflip-flopinvariably exhibitarippleeffect,where false outputcountsaregenerated betweensome steps of thecountsequence. These typesof counter circuits are called asynchronous counters,or ripple counters.

6. When does race conditionarise inanasynchronous sequential circuit?(EI May

2007, May 2006)

Racecondition(race)isaconditioninsequentialcircuitsinwhich twoor more variableschangeatonetime.Inpractice,i.e.withnonidealcircuits,thereisapossibility of incorrect operation undersuch a condition.

7. Definestateassignment. (Nov 2005)

Stateassignmentistheprocessofassignmentofbinary valuestothestatesofthe reduced state tablein thedesign of asynchronous circuits. In synchronous circuits-state assignmentsare madewiththe objective of circuitreduction.Asynchronouscircuits-its objectiveis to avoid critical races.

8. Define cycle. (Nov 2005/Apr2005/Dec13)

Ifan inputchangeinduces afeedback transitions through morethan oneunstable state, then such asituation is called acycle.

9. Definehazard. (EC May 2007/Nov 2005/Nov 2003)

Hazard istheunwantedtransienti.e..Spike orglitch thatoccurs duetounequal propagation delays through acombination circuit.

10. Definea stablestate. (Apr2005)

Thetime sequenceof input, output and FFstates can be enumerated in a statetableit is also called as transition table. Thetablehas four section present states, input, next state and output.

11. What is anasynchronous sequential circuit? (Nov 2004) Solution:

Ifacircuitisnotcontrolled by aclockthetransitionofonestatetonextstateoccur wheneverthereisachangeintheinputtothecircuitatanytimeandhencethiscircuitis called asynchronous sequential circuit.

12. When do hazardoccur? (Nov 2004) Solution:

Inacombinationalnetwork,whichhasseverallogicgatesandseveralpathsfrom

inputtooutput,aninputtothenetworkproducesanoutput. Inpracticedifferentpaths throughthenetworkfrominputterminaltooutputterminalmay havedifferentpropagation delays.Whentheinputchanges,itmay sohappenthatundesirableswitchingtransientsmay appearatthe output.Ifthenetwork isa partofa largerasynchronoussequentialnetwork, switching transientsmay causemalfunctioning ofthe system.Atthisconditionhazardwill occur.

13. Defineglitch. (Apr2004) Solution:

Theunwanted switchingtransients that mayappearat theoutputofa circuit arecalled

glitch orHazards.

14. DefineStatic hazard. (Apr2004) Solution:

Statichazardisacondition,whichresultinasinglemomentaryincorrectoutputdue to changeis a single input variablewhen the outputis expected to remain in thesame state.

15. What is the causefor essential hazard? (Apr2003) Solution:

OperationalerrorgenerallycausedbyanexcessivedelaytoaFeedbackvariablein

responsetoaninputchange,leading toatransitiontoanimproperstate.Forexample,an excessivedelay throughaninvertercircuitincomparisontothedelayassociatedwiththe feedback path maycauseessential hazard.

16. Distinguishbetweenfundamentalmodeand pulse mode circuits. Solution:

Pulse mode / Fundamental mode
Theinputs arepulses, asalready
stated. / Theinputs arelevels, asalreadystated.
Thewidth of theinputpulses is such
that the circuitcanrespond to the inputwithoutdoubt, beforeitpasses off. / Theinputvariables changeonlywhen
the circuitis in stable state.
Pulse width must notbeso longthat
itis still present afterthenew state is / Onlyoneinputvariable can change at
atime.

reached.

17. What arethe two typesofstateassignment? (EI May 2009) Solution:

Two typeof state assignment are

a. Shared-rowstateassignment b. One-hot state assignment

18. What arethe two typesofraces? (Nov 2007) Solution:

a. Critical races

b. Non critical races

19. What is static-1 hazard? Solution:

Iftheoutputmomentarilygoestostatezero‘0’whentheoutputisexpectedtoremain

in ‘1’ as per thesteadystate analysis. Thehazardof this natureis known as static-1 hazard.

20. What are classes ofasynchronous sequential circuits? Apr’10,May 2006)

Therearetwotypesofclassesfundamentalmodeasynchronoussequentialcircuits and pulsemode asynchronous sequential circuits

21. Why do races occurinasynchronous sequential circuits?(May 2007/ Nov 2007/Nov 2006 May 13)

Whentwoormorebinarystatevariableschangetheirvalueinresponsetoachange

in an input variableracecondition occurs in an asynchronous sequential circuit.

22. Drawa scale of8 ripplecounter. (May 2006)

23. What is anasynchronous sequential circuit? (May 2006)

Solution:

Asynchronoussequentialcircuitmemory elementsareeitherunclockedflip-flopsor timedelay elements.Inasynchronoussequentialcircuitchangeininputsignalcanaffect memoryelement at anyinstant of time. Theyaredifficult to design.

24. What is a hazardinasynchronous sequential circuit? (May 2007/ May2008) Solution:

Hazard is aunwanted switchingtransients that mayappear atoutputof the circuitbecausedifferentpaths exhibit different propagation delay.

25. What is excitationtable? (May 2008) Solution:

Excitationtablecontainspresentandnextstatefromwhichwecanfindtheinputofthe flip flop.

26. What is flowtable? (Nov 2007Dec13)

Solution:

Flowtableintheasynchronoussequentialcircuitissameasthatofstatetableinthe synchronoussequentialcircuit.Inasynchronoussequentialcircuitstatetableisknownas

flowtablebecauseofthebehaviorofasynchronoussequentialcircuit.Thestatechange occursindependentofaclockbasedonthelogicpropagationdelay andcausesthestatesto flowfrom one to another.

27. Howraces can beavoided?(Apr’10)

Solution:

Racescan beavoidedby directing thecircuitthroughintermediateunstablestatewith a uniquestate variable change. Whena circuitgoesthrougha uniquesequence of unstable stateitis said to haveacycle.

UNITV -PROGRAMMABLE LOGIC DEVICES, MEMORYANDLOGICFAMILIES

1. What arethe advantages ofCMOS? (Nov 2003,EI Nov 2007)

The advantages of CMOSare

Remarkable low staticPower dissipation.

Its Propagation delayis low with improved noisemargin.

Thesecircuitstake advantage ofthefactthatNMOSand PMOSTransistorscanbe fabricatedonthesamesubstrate.Ithaslowestpackaging density,highspeedand improved noiseimmunity.

2. CompareROMandPROM. (EI Nov 2007)

ROMorReadOnly Memory,Computersalmostalwayscontainasmallamountof read-only memory thatholdsinstructionsforstartingupthecomputer.UnlikeRAM,ROM cannotbewrittento.Itisnon-volatile whichmeansonceyouturnoffthecomputerthe information is still there.

PROM,shortforprogrammableread-only memory APROMisamemory chipon whichdatacanbewrittenonly once.OnceaprogramhasbeenwrittenontoaPROM,it remainsthereforever.UnlikeRAM,PROM'sretaintheircontentswhenthecomputeris

turnedoff.ThedifferencebetweenaPROMandaROM(read-only memory)isthataPROM ismanufacturedasblankmemory,whereasa ROMisprogrammedduringthe manufacturing process.Towrite dataontoa PROMchip,youneeda specialdevice calleda PROM programmeror PROMburner.The process ofprogramminga PROMissometimescalled burningthe PROM.

3. ComparePAL andPLA (EC Nov 2007)

PALis Programmable Array Logic andPLA is ProgrammableLogicArray.In aPLA, boththeOR gatesandtheANDgatescanhavetheirinputsconnectedanddisconnected. Ina PAL,onlytheANDgatescan havetheirinputsconnectedanddisconnected("programmed"). ThismakesPAL deviceseasiertoprogramandlessexpensivethanPLA.Ontheotherhand, sincethe OR arrayis fixed,itis less flexible than aPLA device.

4. Classify the basic families that belong to the bipolar families and to the MOS

families.

TheBipolarlogicfamily isclassifiedintoSaturatedlogicandUnsaturatedlogic.TheRTL, DTL,TTL,I2L,HTLlogiccomesunderthesaturatedlogicfamily.TheSchottky TTL,and ECLlogic comes under theunsaturated logicfamily.

5. What is FPGA? (EI Nov 2007)

FPGA refers toField Programmable Gate Array.The field-programmablegatearray (FPGA)isanintegratedcircuitdesignedto beconfiguredby thecustomerordesignerafter manufacturing—hence"field-programmable".TheFPGAconfigurationisgenerally specified using ahardwaredescriptionlanguage(HDL),similartothatusedforanapplication-specific integratedcircuit(ASIC).FPGAscanbeusedtoimplementanylogicalfunctionthatan ASICcouldperform.Theabilitytoupdatethefunctionalityaftershipping,andthelownon-

recurringengineeringcostsrelativetoanASICdesign(notwithstandingthegenerallyhigher unitcost).

FPGAs contain programmable logic components called "logic blocks", and a hierarchy ofreconfigurableinterconnectsthatallowtheblockstobe"wiredtogether" somewhatlike a one-chipprogrammablebreadboard.Logic blocks canbe configuredto performcomplexcombinationalfunctions,ormerely simplelogicgateslikeANDandXOR.InmostFPGAs,thelogicblocksalsoincludememoryelements,whichmay besimpleflip- flops or more complete blocks ofmemory.

6. Drawthe general structureofPAL. (EI May 2007)

7. Which memory is calledvolatile? Why? (Nov 2005)

RAMiscalledvolatilememory,becausethecontentstoredinthiswillbeerased when power is switchedoff.

8. What is PLA? (Nov 2005/Apr2005)

ProgrammablelogicArray (PLA)isa typeoffixedarchitecturelogicdeviceswith programmable ANDgates followed byprogrammable ORgates.

9. What is a EPROM? (Apr2004/May 2008/May 2011)

EPROMisaprogrammableROMwhosecontentcanbeerasedusing ultravioletrays and the ROM can besubsequentlyprogrammed

10. Howmany address lines are required fora 4KROM?

Therelation between address lines and memorycapacityis

2n =memorycapacity.

Wheren is thenumberof address lines. Therefore2n=4096 gives n=12

No of address lines required=12

11. Defineaddress spaceandmemory space?(EI Dec13)

Invirtualmemory,theusergivesa larger addresscalledvirtualaddress.Asetof such addressesiscalledaddressspace.Theequivalentmainmemory addressgeneratedinthe location ofphysical address. A set of such location is called the memoryspace.

12. What is EEPROM?

EEPROMistheelectricallyerasableprogrammablereadonly memory,whichisan extensionofEPROM.Thespeciality of EEPROMisthatitispossibletoeraseandrestorea single byte separately.

13. What arethe two types ofmemory expansioninRAM?

1.Expandingthe numberof words stored.

2.Increasingthenumberof bits perword.

14. ComparestaticRAMwith dynamic RAM.

Static RAM / DynamicRAM
1. / StaticRAMcanbebuilteitherwith
bipolar transistors or MOS
transistors / DynamicRAM is builtonlywith
MOS transistors.
2. / Static RAMs need morespace, for
the same capacityas dynamicRAMs. / DynamicRAMs areto berefreshed
periodicallywhile, staticRAMs
don’t requirethis.

15. What areadvantages ofPLD’s?

Solution:

a. Reduction in requirementof space

b. Reduction in requirementof power c. Compactness in design

d. High chip density

e.Higher switchingspeed

16. Explainstaticmemory. Definestaticmemory. (May 2007/Nov 2006)

Memoriesthatconsistofcircuitscapableofretainingtheirstateaslongaspoweris applied areknown as static memories. EgRAM

17. What is RAM? (Nov 2006)

We can read fromand writeinto the RAM, so it is called as read/writememory.It is a volatile memory, i.e. itcannot hold data when power is turned off.

18. Mention the two types oferasable PROM. (Nov 2006)

Two types of erasable PROM are EPROM(Erasable programmable Read only memory)and EEPROM(Electrical Erasableprogrammable Read onlymemory)

19. Howis individual location ina EEPROMprogrammedorerased? (May 2006)

Dataisstoredaschargeornochargeonaninsulatedlayer.Theinsulating layeris madeverythinthereforeavoltageaslowas20to25Vcanbeusedtomovechargesacross thethinbarrierineitherdirectionforprogramming or erased.EEPROMallowsselective erasingat theregister level.

20. What is meant by static and dynamicmemories? (May 2006)

Memoriesthatconsistofcircuitscapableofretainingtheirstateaslongaspoweris applied areknown as static memories. DynamicRAM stores the dataas achargein capacitor.

21. WhetherROMis classified as a nonvolatilestoragedevice? Why?(May 2007)

It stores data that are used repeatedlyin system applications such as tables, conversionsorprogrammedinstructionfor systeminitializationandoperations.ROMretains stored data when power is off and arethereforenonvolatilememories.

22. Writethe advantageofEPROMoveraPROM. (May 2007)

InEPROMtheprogramcanbeerasedbyultravioletrayswhileinPROMitnot possible. PROM uses bipolaror MOStechnologybut EPROM uses onlyMOS technology.

23. What is a combinational PLD? (Nov 2007)

PLDisanintegratedcircuitwithinternallogicgatesthatareconnectedthrough electronicpath that behavesimilar to fuses.

24. Showthe circuit ofn-Channel MOSinverter. (EI May 2009)(Reg 2007)

Thebelowfigure showstheNMOSinverterwithresistiveload,RL.Theinputtothe inverterisatthegateoftheN-channeloutputtransistorNOandVIN=VGS.Theoutputisat thedrainandVOUT=VDS=VDD–IRLRL.ForVINVt,NOiscutoffanddoesnotconduct draincurrent.Sincetheresistorcurrentisequaltothedraincurrent,withVINVtIRL=ID(OFF)

=0andtheoutputisVOUT=VDD. Astheinputisincreasedslightlyabovethethreshold voltageNObeginstoconduct.Atthispointonlyasmallcurrentflowsandthedrainvoltage islightly lessthanVDD.AslongasVDS=VGS–Vt,NOisoperatinginthesaturation region. Withfurther increase of the input,a larger draincurrentconductsandthe output voltagecontinuestofall.Insummary,foralowinputtheoutputishigh.Converselyforahigh inputthe output is low.