The C Flag Is Not Affected by the INC Instruction

6. Which of the following is NOT true?
a. The DAA instruction works only on the A accumulator.
b. The DAA instruction is used to adjust the results of additions involving BCD numbers.
c. The DAA instruction adds 6^10(%0110) to any BCD digit that is greater than 9^10-
d. The DAA instruction is used to convert numbers from binary into decimal.
7. The V flag
a. is set if an operation produced a valid result.
b. is set if an operation may have produced and invalid result.
c. is set if the 2's complement system is to be used.
d. is set if unsigned numbers are to be used.
V flag is an indication of overflow.

8. When a flag in CCR is said to be set, its logic state is
a. undetermined
b. logic 0
c. logic 1
d. logic 2
9. The B accumulator already has $07 in it and the Z and C flags are cleared. THe processor then executes the SUBB instruction, in the immediate (IMM) mode. The operand for the instruction is $07. After the instruction is executed, the Z flag will be
a. set
b. cleared
c. undetermined
d. The SUBB instruction does not affect the Z flag.
10. Referring to the conditions in Question 9 above, after the instruction is executed, the C flag will be
a. set
b. cleared
c. undetermined
d. THe SUBB instruction does not affect the Z flag.
11. The D register
a. is an 8-bit register that is separate from the A and B accumulators.
b. is a 16-bit register that is separate from the A and B accumulators.
c. is a 16-bit register that is composed of the A and B accumultors taken together.
d. is a on-bit register set aside for the D flag.
12. A program lists "LDAA #$16" under Source Code. When this instruction is executed
a. accumulator A will contain $16
b. accumulator A will contain the contents of memory location $0016.
c. accumulator A will contain the contents of a memory location whose address is the sum of whatever is in the X index register, plus $16.
d. accumulator A will contain $16 only if the CCR is cleared.
13. Which of the following would NOT involve the ALU?
a. The execution of an ADDA, IMM instruction.
b. The execution of a LDAA, IMM instruction.
c. The execution of a LDAA, INDX instrucion.
d. The execution of the STAA, INDY instruction.
14. Accumulator A is loaded with $00. Accumulator B is then loaded with $FF. After this happens, the N flag will be
a. set
b. cleared
c. set if negative logic is used, or cleared if positive logic is used.
d. set only if the N Code is being used.
15. With the LDAA and LDAB instructions, the direction of the data movement is
a. from memory to a processor register.
b. from a processor register to memory.
c. from one processor register to another.
d. from one memory location to another.
16. When the LDAA instruction s executed, what happens to the data that was originally in the A accumulator?
a. It is stored in the B accumulator.
b. It is stored in the memory location from which the new data for the A was obtained.
c. It is transformed to the CCR.
d. It is lost.
17. When the STAA instruction is executed, what happens to the data that was originally in the A accumulator?
a. It is stored in the B accumulator.
b. It is stored in memory.
c. It is transferred to CCR.
d. It is lost.
18. How does the LDAA instruction affect the C flag?
a. The C flag is always cleared.
b. The C flag is always set.
c. The C flag may be set or cleared, depending on the data that was loaded.
d. The C flag is not affected by the LDAA instruction.
19. Certain instructions execute the next instruction in one memory location or another, depending on the state of specific flags in the CCR. These are known as
a. Load instructions.
b. Store instructions.
c. Add-without-carry instructions.
d. Branch instructions.
20. Each of the load instructions that copies two bytes of data follows the
a. "low-byte first" convention.
b. "high-byte first" convention.
c. "reverse integer" convention.
d. 2's complement convention.
21. The increment instructions that involve the processor registers only use the
a. from one memory location to another, using a single instruction.
b. from the processor registers to memory.
c. from memory to the processor registers.
d. from one processor register to another processor register.
22. The increment instructions that involve the processor registers only use the
a. INH (inherent) addressing mode.
b. IMM(immediate) addressing mode.
c. DIR (direct) addressing mode.
d. These instructions use all the addressing modes.
23. The contents of accumulator A are $FF, and the C flag is cleared. An INCA instruction is executed. The C flag is
a. set
b. cleared
c. cannot be determined
d. added to accumulator A, so that it contains $01.

The C flag is not affected by the INC instruction.