EE 448
Final project report
Changwen Hsieh
USC ID: 8503883891
I. Table of Performance:
Parameter Description / Required / First design simulation / First design hand calculation / Final design simulation / Final design hand calculationPower Supply (nVdd) / 2.5 V / 2.5 V / 2.5 V / 2.5 V / 2.5 V
Transimpedance (dBΩ) / > 60 dB / 60.2 dB / 65 dB / 60.2 dB / 64.7 dB
Bandwidth (W-3dB): / > 2.5 GHz / 2.68 GHz / 273 MHz / 2.54 GHz / 1.6 ~ 6 GHz
Total Equivalent Input Noise Current(from DC to 2.5 GHz) / < 1 uA / 0.9 uA / 1.98 uA / 0.96 uA / 0.584 uA
Total Power Dissipation / < 50 mW / 28.5 mW / 28.5 mW / 13.1 mW / 13.1 mW
Gain-bandwidth product / 2.5*10^(12) / 2.74*10^(12) / 4.85*10^(11) / 2.6*10^(12) / 2.75*10^(12) ~ 1.03*10^(13)
Total capacitor / <= 20 pF / 20 pF / 20 pF / 2.5 pF / 2.5 pF
II. Schematic:
First design:
Final design:
Introduction to the project:
Design a TIA (Transimpedance Amplifier) using 0.25 um CMOS process technology with following specifications and constraints:
III. TIA design and simulations of original design
- design strategy & Hand Calculation:
The strategy of my original design has 3 stages. I use the structure connecting two transistors together at first stage because I found out that this structure has zeros and I could build a 55dB and W-3db= 2.7GHz stage by using this structure. For high gain and wide bandwidth, transistor M1 should be larger and M2 should be smaller because 1/(gm2+gmb2) is small and it can decrease time constant at the node of gate of M1. However, there is no such advantage of Cgd2. If we choose large size of M2, time constant at the node of drain of M2 would be large. Therefore, M2 should be chosen as small size.
Schematic of first stage:
Simulation result of first stage(without feedback):
Gain = 58.8 dB, BW-3dB= 2.66 GHz
At second stage,I use a cascode with feedback to increase some gain and make sure bandwidth is still large enough. It should be notice that the value of Rf is larger, gain is larger but bandwidth would be smaller, vice versa.
Schematic of second stage:
However, gain is still not enough. Therefore, I use a simple common source amplifier and followed by a common drain(buffer) as my last stage. For the common source amplifier, I do not use cascade because the gain here is not large. If I use cascade, total capacitor would be larger than simple common source.
Schematic of third stage:
b. A print-out of the HSPICE netlist. (Changwen_Hsieh.lib)
* Design Team Members: Changwen Hsieh
* Design Specifications: single-ended, AC-coupled
.SUBCKTTIAnIinnVoutnVddnGND
*1st stage
Cbig nIin s3 13pF
M1d1ng1nGND nGNDCMOSNW=80uL=0.25u
R1 nvdd d1 1.9k
M2d2d1ng1 nGNDCMOSNW=10uL=0.25u
R2 nvdd d2 1k
M3 ng1 g3 s3 nGND CMOSNW=70uL=0.25u
RB1 nvdd g3 16k
RB2 g3 nGND 9k
C3 g3 nGND 3p
*bias
M41 g4 g4 nGND nGND CMOSNW=50uL=0.25u
M42 s3 g4 nGND nGND CMOSNW=63uL=0.25u
*I4 nvdd g4 1m
R41 nvdd g4 1.828k
C4 g4 nvdd 1p
*2nd stage
M5 nvdd d2 s5 nGND CMOSNW=25uL=0.25u
R5 s5 nGND 3k
M6 d6 s5 nGND nGND CMOSNW=30uL=0.25u
R7 nvdd d7 2k
M7 d7 g7 d6 nGnd CMOSNW=8uL=0.25u
RB71 nvdd g7 10k
RB72 g7 nGnd 15k
C7 g7 nGnd 3p
*feedback
Rf d7 d2 5k
*3rd stage
M8 d8 d7 nGND nGND CMOSN W=8uL=0.25u
R8 nvdd d8 0.8k
M10nvddd8nvout nGNDCMOSN W=32uL=0.25u
R10 nvout nGND 5k
.ENDS
- A print-out of the HSPICE output file
d. An HSPICE print-out of small-signal gain magnitude versus frequency.
BW-3db = 2.68GHz
e. An HSPICE print-out of the output and input transient analysis
(334-323)*10^(-3) / 10*10^(-6) = 1100
20 * Log(1100) = 60.8 dBΩ
Run more periods to make sure it’s stable
f. An HSPICE print-out of the noise analysis
1 ****** HSPICE --- Y-2006.09 32-BIT (Aug 25 2006) 15:51:45 11/30/2010 solari
******
* test bench for tia design
****** noise analysis tnom= 25.000 temp= 25.000
******
frequency = 2.5119g hz
**** resistor squared noise voltages (sq v/hz)
element 0:rload 1:r1 1:r2 1:rb1 1:rb2
rs 3.778e-19 3.3362a 17.7042a 1.504e-20 2.674e-20
1/f 0. 0. 0. 0. 0.
total 3.778e-19 3.3362a 17.7042a 1.504e-20 2.674e-20
rx 33.8723 620.4662 1.0369k 120.8980 120.8980
element 1:r41 1:r5 1:r7 1:rb71 1:rb72
rs 7.851e-19 2.1137a 2.1291a 8.902e-23 5.934e-23
1/f 0. 0. 0. 0. 0.
total .851e-19 2.1137a 2.1291a 8.902e-23 5.934e-23
rx 295.2389 620.5859 508.5386 7.3528 7.3528
element 1:rf 1:r8 1:r10
rs 4.5995a 5.913e-19 3.778e-21
1/f 0. 0. 0.
total 4.5995a 5.913e-19 3.778e-21
rx 1.1818k 169.4922 33.8723
**** mosfet squared noise voltages (sq v/hz)
element 1:m1 1:m2 1:m3 1:m41 1:m42
rd 0. 0. 0. 0. 0.
rs 0. 0. 0. 0. 0.
id 35.0618a 22.0276a 92.3355a 9.4684a 77.3891a
rx 620.4662 775.9948 854.8858 295.2389 808.6018
fn 0. 0. 0. 0. 0.
total 35.0618a 22.0276a 92.3355a 9.4684a 77.3891a
element 1:m5 1:m6 1:m7 1:m8 1:m10
rd 0. 0. 0. 0. 0.
rs 0. 0. 0. 0. 0.
id 14.8348a 11.2883a 1.2665a 9.084e-19 1.563e-19
rx 620.5859 397.3669 207.8621 169.4922 33.8723
fn 0. 0. 0. 0. 0.
total 14.8348a 11.2883a 1.2665a 9.084e-19 1.563e-19
**** total output noise voltage = 296.4193a sq v/hz
= 17.2168n v/rt hz
transfer function value:
v(nrl)/iin = 778.6537
equivalent input noise at iin
= 22.1110p /rt hz
**** the results of the sqrt of integral (v**2 / freq)
from fstart upto 2.5119g hz. using more freq points
results in more accurate total noise values.
**** total output noise voltage = 852.1204u volts
**** total equivalent input noise = 906.2795n
IV. TIA design and simulations of final design
- design strategy & Hand Calculation:
After presentation, I follow professor’sadvice, fix my original design and redo the hand calculation.
The strategy of my final design has 3 stages. In the first stage, I still use the same structure as my original one because this structure has zeros and it could increase bandwidth. I substitute the Ibias to a resister Rb and I reduce M1’s size because the total capacitance at the node would decrease, and then it would decrease time constant and increase bandwidth.
In hand calculation, there are three zeros, two are complex conjugate at 7.84*10^9 +i*5.56*10^10 (rad/s) and one zeros is at 978MHz. And there are two poles at 800 MHz and 239 GHz.
Gain = 63 dB, BW-3dB= 2.9 GHz. Slope is -60dB/dec. There are 3 poles at 2.9GHz
I connect the output of the first stage to a buffer and then connect to the second stage. I followed professor’s advice to take out the feedback. I use a common source with degeneration and add a capacitor parallel with the degeneration resistor. I use this structure because it would create two zeros through this structure and increase bandwidth.
And then I connect the output of this stage to a buffer.
In hand calculation, there are two zeros at this topology. + 557 MHz.
And there are two complex conjugate poles at 6 GHz.
At last stage (3rd stage), I use the same topology as 2ns stage, and connect a buffer to the output.
In hand calculation, there are two zeros at this topology. One is at 64 GHz and another one is at 1.6GHz.And there are two poles at 414 MHz and 10 GHz.
b. A print-out of the HSPICE netlist. (Changwen_Hsieh.lib)
.SUBCKTTIAnIinnVoutnVddnGND
*1st stage
M1d1nIinnGND nGNDCMOSNW=20uL=0.25u
R1 nvdd d1 2.5k
M2d2d1nIin nGNDCMOSNW=10uL=0.25u
R2 nvdd d2 1.5k
Rb nIin ngnd 1k
*buffer
M3 nvdd d2 s3 nGND CMOSNW=10uL=0.25u
R3 s3 nGND 2k
*2nd stage
M4 d4 s3 s4 nGND CMOSNW=30uL=0.25u
Rs4 s4 nGND 150
C4 s4 nGND 1.5p
R4 nvdd d4 1.2k
*buffer
M5 nvdd d4 s5 nGND CMOSNW=10uL=0.25u
R5 s5 nGND 2k
*3rd stage
M6 d6 s5 s6 nGND CMOSN W=30uL=0.25u
R6 nvdd d6 0.6k
Rs6 s6 ngnd 100
C6 s6 nGND 1p
*buffer
M7 nvdd d6 nvout nGND CMOSN W=34u L=0.25u
R7 nvout nGND 0.5k
.ENDS
c. A print-out of the HSPICE output file
d. An HSPICE print-out of small-signal gain magnitude versus frequency.
Gain = 60.2 dB, BW-3dB= 2.54 GHz. Slope is -100dB/dec. There are 5 poles at 2.9GHz
e. An HSPICE print-out of the output and input transient analysis
(-43.4)*10^(-6)+(10.1)*10^(-3) / 10*10^(-6) = 1005.66
20 * Log(1100) = 60.05 dBΩ
Run more periods to make sure it’s stable
f. An HSPICE print-out of the noise analysis
****** HSPICE --- Y-2006.09 32-BIT (Aug 25 2006) 22:43:55 12/05/2010 solari
******
* test bench for tia design
****** noise analysis tnom= 25.000 temp= 25.000
******
frequency = 2.5119g hz
**** resistor squared noise voltages (sq v/hz)
element 0:rload 1:r1 1:r2 1:rb 1:r3
rs 3.818e-19 19.7231a 4.2349a 9.2408a 8.739e-19
1/f 0. 0. 0. 0. 0.
total 3.818e-19 19.7231a 4.2349a 9.2408a 8.739e-19
rx 34.0486 1.7305k 621.1321 749.1538 325.8104
element 1:rs4 1:r4 1:r5 1:r6 1:rs6
rs 1.936e-19 6.072e-19 1.924e-19 2.146e-19 1.428e-19
1/f 0. 0. 0. 0. 0.
total 1.936e-19 6.072e-19 1.924e-19 2.146e-19 1.428e-19
rx 41.9942 210.3727 152.8923 88.4218 29.4541
element 1:r7
rs 3.818e-20
1/f 0.
total 3.818e-20
rx 34.0486
**** mosfet squared noise voltages (sq v/hz)
element 1:m1 1:m2 1:m3 1:m4 1:m5
rd 0. 0. 0. 0. 0.
rs 0. 0. 0. 0. 0.
id 127.1958a 17.4385a 2.8980a 2.6586a 6.963e-19
rx 1.7305k 736.0214 325.8104 206.8018 152.8923
fn 0. 0. 0. 0. 0.
total 127.1958a 17.4385a 2.8980a 2.6586a 6.963e-19
element 1:m6 1:m7
rd 0. 0.
rs 0. 0.
id 5.137e-19 1.159e-19
rx 75.2066 34.0486
fn 0. 0.
total 5.137e-19 1.159e-19
**** total output noise voltage = 187.3603a sq v/hz
= 13.6880n v/rt hz
transfer function value:
v(nrl)/iin = 749.1538
equivalent input noise at iin
= 18.2712p /rt hz
**** the results of the sqrt of integral (v**2 / freq)
from fstart upto 2.5119g hz. using more freq points
results in more accurate total noise values.
**** total output noise voltage = 679.1134u volts
**** total equivalent input noise = 584.0632n
V. Discussions
- Agreement or discrepancy between hand analysis,and simulations of first design
Comparison between hand calculation and simulation
The result between hand calculation and simulation has some discrepancy of bandwidth and noise analysis.
In my hand calculation, bandwidth is 273 MHz. However, it’s 2.68 GHz in simulation. The reason could be the pole in first stage because pole in first stage is major pole. In the first stage there should be 2 zero eliminating effects of poles. Therefore, I could get a 58.8 dB with BW = 2.66 GHz of the first stage in simulation. However, in hand calculation, zeros are at 15.9 GHz and 97.3 GHz while poles are at 488 MHz and 10.4GHz.
For this original design, I believe that I do the wrong hand of bandwidth calculation of stage 1 because I did not include Cin in the calculation. This is the main reason of discrepancy of first design.
For gain part, the value in hand calculation is 65 dB and it’s 60.2 dB in simulation.
For noise part, the value of noise in hand calculation is 1.98 uA and it’s 0.9 uA in simulation.
The reason for these two parts could be that I use approximation in my hand calculation, that is, I ignore some second order effect in hand calculation. It affects those results.
Result of only first stage: (without feedback)
Gain = 58.8 dB, BW-3dB = 2.68 GHz
- Agreement or discrepancy between hand analysis, and simulations of final design
Comparison between hand calculation and simulation
The result between hand calculation and simulation has some discrepancyof bandwidth and noise analysis and little discrepancy of gain.
In my hand calculation, bandwidth is in the middle of 1.6 GHz to 6 GHz, and it’s 2.5 GHz in simulation. The reason could be that I ignore some parallel capacitance in hand calculation.
For noise part, the value of noise in hand calculation is 0.96 uA and it’s 0.584 uA in simulation. The reason could be that I ignore the ro and second order effect in hand calculation.
More, for gain part, the value in hand calculation is 64.7 dB and it’s 60.2 dB in simulation. The reason could be the same as the noise part; I ignore ro and second order effect in hand calculation.