Project PlanRev. 0.5Page 1

Project Meadowlark

University of Portland / School of EngineeringPhone 503 943 7314
5000 N. Willamette Blvd.Fax 503 943 7316
Portland, OR97203-5798

Project Plan

Project Meadowlark: A CMOS Programmable Digital Low-Pass Filter

Contributors:

Jennifer Galaway

Jennifer Williams

Approvals

Name / Date / Name / Date
Signature file / Date / Signature file / Date
Dr. Osterberg / Dr. Lillevik

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University of PortlandSchool of EngineeringContact: J. GALAWAY

Project PlanRev. 1.oPage 1

Project Meadowlark

Revision History

Rev. / Date / Author / Reason for Changes
0.5 / 10/23/02 / J. Galaway and
J. Williams / Initial Draft
0.9 / 10/24/02 / J. Galaway and
J. Williams / Inserted Microsoft Project schedule, budget, updated Table of Contents
1.0 / 10/29/02 / J. Galaway and
J. Williams / Miscellaneous corrections; Advisor and Industry rep approval meeting
1.1 / 11/11/02 / J. Galaway and J. Williams / Change Control Request and Approval

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University of PortlandSchool of EngineeringContact: J. GALAWAY

Project PlanRev. 1.oPage 1

Project Meadowlark

Table of Contents

Summary

Introduction

Product Overview

General Description

Deliverables

Development Process

General Approach......

Assumptions

Milestones

Schedule

Resources

Personnel

Budget

Equipment

Facilities

Risks and Contingencies

Conclusions

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University of PortlandSchool of EngineeringContact: J. GALAWAY

Project PlanRev. 1.oPage 1

Project Meadowlark

List of Figures

Figure 1. Block Diagram of Meadowlark System...... 4

Figure 2. Block Diagram of Meadowlark Digital Filter Chip…………………………………………….5

Figure 3. Meadowlark Schedule ……….………………………………………………………………....10

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University of PortlandSchool of EngineeringContact: J. GALAWAY

Project PlanRev. 1.oPage 1

Project Meadowlark

List of Tables

Table 1. Meadowlark deliverables...... 5

Table 2. Key Meadowlark milestones...... 8

Table 3. Overall Meadowlark budget...... 11

Table 4. Meadowlark project risks…………………………………………………………………………...12

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University of PortlandSchool of EngineeringContact: J. GALAWAY

Project PlanRev. 1.oPage 1

Project Meadowlark

Chapter / Summary
1

The purpose of Project Meadowlark is to build a prototype of a classroom-based demonstration tool when discussing digital filters. Project Meadowlark will display the frequency response of a digital low-pass filter for a 1st, 2nd, or 3rd order filter on a spectrum analyzer. Included in this document are block diagrams of the entire Project Meadowlark system and of the digital filter itself.

There are many deliverables available from Project Meadowlark. These deliverables mostly include hardware, but the one deliverable that is software-based is the tpr netlist file that is used to fabricate the chip.

The tpr file is the key to a properly functioning chip. One of our risks is that our chip will not work properly when we receive it from MOSIS. However, this risk is very low because we will have a macro model available to use in place of the chip. Other risks involve certain parts of Project Meadowlark not functioning properly, such as the spectrum analyzer, DAC, and ADC; as well as Project Meadowlark in its entirety not functioning properly.

The general approach to working on Project Meadowlark is reflected in our schedule. The design work, simulations, ordering of parts, and chip programming will all be completed by the end of fall semester. Spring semester involves building the macro model, testing, and a final presentation and report. Included throughout both semesters are various documents that must be completed by set deadlines.

Project Meadowlark requires very little equipment and facilities provided by the University of Portland. UP will provide the spectrum analyzer and the use of the Electrical Circuits laboratory. In terms of budget, Project Meadowlark is originally set to cost approximately $195, within the limit of $200 provided to us.

Project Meadowlark has a defined schedule that the team members strongly feel that they can meet. Any more information or questions may be directed to Jennifer Galaway or

Jennifer Williams.

Chapter / Introduction
2

The purpose of this document is to layout a project schedule and budget and to assess any risks that may occur and the contingencies of these risks. In completing this document our goal is to be better organized for the months that lie ahead in completing Project Meadowlark.

The intended audience of this Project Plan is our EE/CS 480 classmates; our advisor, Dr. Osterberg; our industry representative, Mr. Michael Desmith; and our EE/CS 480 instructor, Dr. Lillevik.

Later in this document the following sections are discussed:

  • Product Overview: Gives the reader a general description of Project Meadowlark and the deliverables of the project.
  • Development Process: Includes our general approach to Project Meadowlark, assumptions made, milestones, risks, a schedule, resources, and contingencies of the risks.
  • Conclusion: Recaps key points of this document.

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University of PortlandSchool of EngineeringContact: J. GALAWAY

Project PlanRev. 1.oPage 1

Project Meadowlark

Chapter / Product Overview
3

General Description

Figure 1 shows the overall setup of Project Meadowlark. The function generator sends out an analog signal of sweeping sine waves, which enters an Analog-to-Digital Converter (ADC). This converts the analog signal into an 8-bit digital signal, which enters the Digital Filter chip (See Figure 2 for the Chip Block Diagram). Other inputs into the chip are three coefficients of a difference equation. Once the signal is properly filtered, another 8-bit digital signal enters a Digital-to-Analog Converter (DAC), which allows the newly filtered digital signal to be converted back into an analog signal. The output of the DAC is inputted into the Oscilloscope, and a graph is shown, depicting the magnitude of the frequency response of the digital filter.

Figure 1. Block Diagram of Meadowlark System


Figure 2. Block Diagram of Meadowlark Digital Filter Chip

Deliverables

Table 1. Meadowlark deliverables.

Number / Deliverable
1 / Function Generator and Oscilloscope experiment
2 / Chip Design and Simulation
3 / Chip tpr file completed
4 / Lock DAC and ADC choices
5 / Order Parts
6 / Macro Model
7 / Prototype Assembly and debugging with the Macro Model
8 / Receive Chip and Plug-In
9 / Final Functional Prototype and Demonstration

Function Generator and Oscilloscope Experiment

We will be conducting an experiment to verify our expected results of our project using a simple resistor and capacitor circuit.

Chip Design and Simulation

This involves breaking down the larger parts of Project Meadowlark into their simplest logic gates and simulating it in B2Logic.

Chip tpr file completed

Completed netlist file for the chip in order to be programmed by MOSIS.

Lock DAC and ADC choices

Decide which type of DAC and ADC will work best with our design.

Order Parts

Order all the parts that we need for our Macro Model.

Macro Model

Build the Macro Model of Project Meadowlark.

Prototype Assembly and Debugging with the Macro Model

Put together all pieces of Project Meadowlark and test it with the Macro Model.

Receive Chip and Plug-In

Take away the Macro Model and plug in the chip to see if Project Meadowlark still functions properly with the chip.

Final Functional Prototype and Demonstration

Completed and fully tested prototype of Project Meadowlark.

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University of PortlandSchool of EngineeringContact: J. GALAWAY

Project PlanRev. 1.oPage 1

Project Meadowlark

Chapter / Development Process
4

General Approach

Our overall goal is to get everything done as soon as possible. The first step we have already completed, this being conducting research about digital filters, specifically about how they work. The next step is to perform a Spectrum Analyzer simulation of a digital filter to confirm our expected results graphically. Next will be designing the individual parts of the project broken down into their simplest logic gates. We will then take this design and input this into B2Logic to simulate Project Meadowlark. After B2Logic confirms our expected results, we will use this schematic to write the .tpr file for the MOSIS chip. While one team member completes this task, the other team member will order parts necessary to build the macro model of Project Meadowlark. After these parts are received, we will build the macro model and test it. Once the chip is sent to us from MOSIS, we will plug it in to our model and see if our .tpr file was successfully programmed. After this, there will be some more testing leading up to the final presentation of Project Meadowlark.

Assumptions

Function Generator and Oscilloscope work properly

ADC and DAC work with our design

MOSIS chip works properly

Milestones

Table 2. Key Meadowlark milestones.

Number / Description / Original
Date / Previous
Date / Present
Date
1 / Product Approval / 10/04/02 / 10/04/02 / 10/04/02
2 / Project Plan Approval / 10/25/02 / 10/25/02 / 10/29/02
3 / Function Generator and Oscilloscope Experiment / 11/01/02 / 11/01/02 / 11/01/02
4 / Design Review Meeting / 11/22/02 / 11/22/02 / 12/05/02
5 / tpr File Completed / 11/27/02 / 11/27/02 / 12/06/02
6 / Design Release / 12/06/02 / 12/06/02 / 12/06/02
7 / TOP Approval / 02/14/03 / 02/14/03 / 02/14/03
8 / Macro Model Complete / 02/07/03 / 02/07/03 / 02/07/03
9 / Prototype Functional with Macro Model / 03/07/03 / 03/07/03 / 03/07/03
10 / Receive MOSIS chip / 03/17/03 / 03/17/03 / 03/17/03
11 / Prototype Release / 04/04/03 / 04/04/03 / 04/04/03
12 / Founder’s Day Presentation / 04/07/03 / 04/07/03 / 04/07/03
13 / Post Mortem Presentation / 04/22/03 / 04/22/03 / 04/22/03
14 / Final Report / 04/25/03 / 04/25/03 / 04/25/03

Table 2 lists the key Project Meadowlark milestones. The Product Approval was the first milestone completed. The Project Plan Approval is in essence just an approval of this document. The Function Generator and Oscilloscope experiment is to give us confidence in our design and the outcome. The Design Review Meeting is to have a face-to-face meeting with our industry rep and show him all aspects of our design. Completing the tpr file must be done before the end of the semester in order to receive the chip in time. The Design Release finalizes our design. Any further changes will be taken to the Change Control Board. The TOP Approval is an approval of our Theory of Operation document to be completed in the spring. Completing the Macro Model requires weeks of building a “backup plan” in essence, as a contingency plan for the risk of our chip not working properly. Having the Prototype functional with the Macro Model is the next milestone. This is essential for our contingency plan to work. Receiving the MOSIS chip marks the day that we can plug in our chip to our system and see if the chip was successfully programmed. The Prototype Release is the day where we are required to have a working demonstration of our project before Founder’s Day, where we will conduct formal presentations. Post Mortem is a presentation to future Senior Design students, giving them advice for their projects. The final report is a summary of all of the work completed throughout the year.

Schedule

Figure 3. Meadowlark schedule

Resources

Personnel

Jennifer Galaway: Team Leader for Fall Semester; Programming .tpr file, designing, spectrum analyzer simulation, B2Logic simulation, build macro model, testing.

Jennifer Williams: Team Leader for Spring Semester; Choosing parts, website, designing, spectrum analyzer simulation, B2Logic simulation, build macro model, testing.

Budget

Table 3. Overall Meadowlark budget

1 / Materials / Subtotal / $195
1.1 / ADC / 1 / (est) $15 / $15
1.2 / DAC / 1 / (est) $15 / $15
1.3 / wires / 1 set / (est) $20 / $20
1.4 / wire wrapping gun / 1 / (est) $80 / $80
1.5 / wire stripper / 1 / (est) $25 / $25
1.6 / Logic gates / unknown / $0 / $0
1.7 / Resistors / unknown / $0 / $0
1.8 / Capacitors / unknown / $0 / $0
1.9 / Bread board / 1 / (est) $15 / $15
1.1 / Power supply / 1 / (est) $10 / $10
Switches (8-bit) / 3 / (est) $5 / $15
2 / Services / Subtotal / $0
2.1 / Fabrication / 1 / $0 / $0
4 / (est) TOTAL / $195

Equipment

  • Oscilloscope: Used to display the final graphical output of Project Meadowlark.
  • ADC (Analog to Digital Converter). Used to convert incoming signal into 8-bits for digital processing within chip.
  • DAC (Digital to Analog Converter). Used to convert outgoing signal into analog for display on spectrum analyzer.
  • Power Supply. Used to power DAC & ADC and Macro Model and chip.
  • Switches. Used to control 8-bit coefficients going into chip.
  • Wire Wrapping Gun. Used to connect pins and wires in macro model and final project.
  • Wire Stripper. Used to prepare wires for wire wrapping.
  • Wires. Used to connect components of project.
  • Logic Gates. Used in macro model and final project construction.
  • Resistors & Capacitors. Used in macro model and final project construction.
  • Bread Board. Used as the base which the macro model and final project will be assembled on.

Facilities

  • Use of the University of Portland School of Engineering Electrical Circuits laboratory when conducting testing and experiments with the equipment listed above.

Risks and Contingencies

Table 4. Meadowlark Project Risks.

Number / Severity / Description
1 / Low / Chip doesn’t work
2 / Low / ADC, DAC doesn’t fit with our design
3 / Medium / Function Generator and Oscilloscope don’t work properly
4 / Low to Medium / Final Prototype doesn’t work properly

Table 4 lists the Meadowlark project risks. Having the chip not work is a low severity risk because we are building a macro model to compensate for this problem. The ADC and DAC not being the best for our design we feel is low severity because we will spend hours researching this and feel that we will be able to secure those parts. The function generator and oscilloscope not working properly is a medium risk because this could change our display, but we feel that they will most likely work well enough so that our display will not be drastically changed. The final prototype working properly is a low to medium risk because our grade could suffer if it does not, but we are confident that Project Meadowlark will be a success.

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University of PortlandSchool of EngineeringContact: J. GALAWAY

Project PlanRev. 1.oPage 1

Project Meadowlark

Chapter / Conclusions
5

Unfortunately, there is a small amount of time to complete Project Meadowlark. Most of our work will come in November, where we need to run a Function Generator and Oscilloscope simulation, design our project, run a B2Logic simulation, and program the tpr file, all before the end of the semester.

We only have a few assumptions, which helps the strength of Project Meadowlark. All of these assumptions can be reflected as risks. Therefore, there are few risks and contingencies involved in Project Meadowlark. However, serious problems could arise if some of these risks come into effect. We are confident that we will be able to eliminate these risks and that Project Meadowlark will be successful.

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University of PortlandSchool of EngineeringContact: J. GALAWAY