Dissertation: Integrated Circuits Outlier Identification by Multiple Parameter Correlation

Sagar Sabade

1520 Richardson Dr. #924
Richardson, TX75080
E-mail: / Phone: (H) 972-231-9724
(W) 214-480-4616
Fax: 214-480-2356

OBJECTIVETo obtain a position as a technical staff in VLSI design, test, design for test (DFT) or CAD related area, with a challenging career and scope for innovation

INTERESTSDesign and testing of VLSI chips, burn-in reduction alternatives, test cost reduction, DFT, test data analysis, ATPG, defect diagnosis

EDUCATION

May 2004Ph.D. (Computer Engineering), TexasA&MUniversity, College Station, TX

Dissertation: Integrated Circuits outlier identification by multiple parameter correlation

Advisor: Dr. Duncan M. (Hank) Walker

Jan. 1996 M. Tech. (Electronics Design & Technology), Indian Institute of Science, Bangalore, India

Project: Space phasor-based V/f controller for 3- induction motor using Intel 80196

Aug. 1994 B.E. (Instrumentation), Govt. College of Engineering, Pune, India

Project: Microprocessor-based PID controller

INDUSTRIAL EXPERIENCE

May 2004 – present DFT Lead Engineer, Texas Instruments, (ASIC Test Services Team), Dallas, TX

Responsible for development and execution of test plans for 3 high-speed, complex ASICs. Leading the development team for DFT strategy in complex chips.

May – Aug 2001Summer Intern, Texas Instruments, (TestTechnologyCenter),Dallas, TX

Developed a web-based statistical data analysis tool for analyzing test data.

Designed and implemented the interface between the Web server and Testware database.

Analysis tool used by test engineers for pass/fail threshold selection in the test flow.

Jun – Aug 2000Summer Intern, Texas Instruments, (Design, Test & Technology Group),Dallas, TX

Assisted production run of logic bit mapping tool for defect diagnosis and yield enhancement

Involved in statistical clustering analysis of IDDQ test data.

Developed scripts for performance comparison of two ATPG tools from different vendors.

Feb 96 – Jun 1999Senior ASIC Design Engineer, CG-CoreEl Logic Systems(now Conexant), Pune, India

Designed, developed and verified ASICs and IP for ATM and SONET applications.

Team leader for T3E3 project – a chip that combined E3 and T3 functionalities.

Responsible for functional validation, timing verification, test bench design, test vector generation and

verification for this 120K gate 0.6 design. This chip was used in ATM Network.

Determined Focused Ion Beam (FIB) edits to eliminate bugs found in an earlier chip after board level

testing and validated these FIBs on the gate level netlist.

Mentored two trainee engineers from 1997-1999 for IP development.

ACADEMIC/RESEARCH EXPERIENCE

Sep 99 – present Research Assistant, Dept. of Computer Science, TexasA&MUniversity

Substitute/guest lecturer for many undergraduate classes on behalf of Dr. Hank Walker.

Jan 99 – May 1999Visiting lecturer, Electronics Dept., Govt. College of Engineering, Pune.

Conducted post-graduate classes for CAD for VLSI course.

Jan 97 – Mar 1997Visiting lecturer, Instrumentation and Control Dept., Govt. College of Engineering, Pune.

Conducted undergraduate classes for Instrument and System Design course.

PROFESSIONAL SERVICE

Referee for International Test Conference, VLSI Test Symposium, VLSI Design Conference and Asia

South Pacific Design Automation Conference, Defect and Fault Tolerance on VLSI Systems, IEEE Transactions for Semiconductor Manufacturing, Computer Aided Design and VLSI Systems

CLASS PROJECTSStudied the effect of process variation on interconnects using Arcadia for RC extraction and static

timing analysis tool PrimeTime.

Developed a Pre-Synthesis Design Rule Check (DRC) Tool using Tcl/Tk.

Developed a web-based class evaluation software (team size of 4).

Directed a class project for Software Engineering class (team size of 22) - a Web-based tool to

monitor and quantify the software development process.

PUBLICATIONS

(Coauthored with D. M. H. Walker, unless marked with *. Published papers are available upon request.)

Journal/Magazines

1. “IDDQ Test: Will it Survive the DSM Challenge?,” IEEE Design and Test of Computers, Special issue on Defect-oriented Testing in the DSM Era, vol. 19, no. 5, Sep/Oct. 2002, pp. 8-16.
2. “Estimation of Fault-free Leakage Using Wafer-level Spatial Information,” IEEE Transactions on VLSI Systems (under review).
3. “IDDX-based Test Methods: A Survey,” ACM Transactions on Design Automation, vol. 9, no. 2, Apr. 2004, pp. 1-39.
4. “IDDQ Data Analysis Using Neighbor Current Ratios,” Journal of System Architecture (Special issue on Design and Test of SoCs), vol. 50, no. 5, Apr. 2004, pp. 287-294.
5. “Leakage Current-based Testing of CMOS ICs,” IEEE Potentials, vol. 23, no. 2, Apr.-May 2004, pp. 28-32.*

Conferences/Workshops

1. “Improved Wafer-level Spatial Information for IDDQ Limit Setting,” IEEE Intl. Test Conference, Baltimore, MD, Oct. 2001, pp. 82-91.

1. “Evaluation of Outlier Rejection Methods for IDDQ Limit Setting,” IEEEVLSI Design/ASP DAC, Bangalore, India, Jan 2002, pp. 755-760.
2. “Evaluation of Effectiveness of MAD Outlier Rejection-based IDDQ Testing for Burn-in Reduction,” IEEE VLSI Test Symposium, Monterey, CA, Apr. 2002, pp. 81-86.
3. “Neighbor Current Ratios (NCR): A New Metric for IDDQ Data Analysis,” IEEE Intl. Symposium on Defect and Fault Tolerance in VLSI Systems,Vancouver, Canada, Nov. 2002., pp. 381-389
4. “Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification,” IEEE VLSI Design Conference, New Delhi, India, Jan 2003, pp. 361-366.
5. “Use of Multiple IDDQ Test Metrics for Outlier Identification,” IEEE VLSI Test Symposium, Napa Valley, CA, Apr. 2003, pp. 31-38.
6. “Wafer-level Spatial and Flush Delay Correlation Analysis for IDDQ Estimation,” IEEE Intl. Workshop on Defect Based Testing, Monterey, CA, Apr. 2002, pp. 47-52.
7. “NCR: A Self-scaling, Self-calibrated Metric for IDDQ Outlier Identification,” IEEE 45th Midwest Symposium on Circuit and System, Tulsa, Aug. 2002, pp. 392-395.
8. “Wafer Signature Analysis of IDDQ Test Data,” IEEE Intl. Workshop on Defect Based Testing, Napa Valley, CA, Apr. 2003, pp. 59-64.
9. “CROWNE: Current Ratio Outliers With Neighbor Estimator,” IEEE Intl. Symposium on Defect and Fault Tolerance in VLSI Systems,Boston, MA, Nov. 2003, pp. 132-139.
10. “Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests,” IEEE VLSI Design Conference, Mumbai, India, Jan. 2004, pp. 889-894.
11. “On Comparison of NCR Effectiveness With a Reduced Vector Set,” IEEE VLSI Test Symposium, Napa Valley, CA, Apr. 2004, pp. 65-70.
12. “Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR Vs NCR,” IEEE Intl. Workshop on Defect Based Testing, Napa Valley, CA, Apr. 2004, pp. 17-22.

HONORSNational Merit Scholar (1988-1994)

University Grants Commission Fellowship (1994-1996)

First rank in the university in Instrumentation Branch (1992-1994)

Recipient of TAMU International Education Study grant (2001)

SKILL SETLanguages: VHDL, Verilog, Perl, Tcl/Tk, Awk, C, Javascript

Tools: Model Tech. VHDL Simulator, Synopsys® Design Compiler, PrimeTime,

Mentor Graphics Fastscan®, BSD Architect, DFT Advisor

Software: SAS, Origin Lab, Gnuplot, Matlab