Department of Electrical and Computer Engineering
COEN 451 April 25, 2008
Answer all Questions. All Questions carry equal marks
Exam Duration 3 hour
You may use the crib sheet and CMOSIS5B parameters attached.
Only recommended calculators are allowed.
No cell phones are allowed even if they are off.
No books, papers are allowed.
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Question1
In this question the MOS transistors have the following parameters:
NMOS
VTO = 0.6V, TOX= 100Ao, mo=550cm2/V-sec, g =0.61V1/2, Cj=7.0X10-4 F/m2,
Cjsw = 1.5EX10-10 F/m, l = 0.033V-1, Fs=-0.6V.
PMOS
VTO = -0.6V, TOX= 100Ao, mo=150cm2/V-sec, g =0.61V1/2, Cj=7.0X10-4F/m2,
Cjsw = 1.5X10-10 F/m, l = 0.033V-1, Fs= 0.6V.
a. Construct a Complex CMOS gate at the transistor level for the following function:
F (A,B,C,D) = AB + C + D
Assume you have double rail (inputs and their complements are available).
b. Determine width of all transistors (in terms of Wn, min) for equal rise and fall time at the output.
c. Assume all transistors have equal L and equal W/L = 4. An input pattern of
A=B=C=D= 0 is applied to the gate, determine the pull down resistance.
d. What would the pull down resistance be, if the input pattern of A=B=C= 0, D=1 is applied to the gate.
Question 2
An engineer wishes to submit the layout shown in Fig. Q2 for fabrication using N-well three- layer metal process:
a. Draw the vertical cross section B-B’ showing (annotate) all layers and material involved.
b. List the sequence of steps up the formation of metal contacts required to fabricate the PMOS transistor in the targeted technology.
c. How many layers of metal appear in the layout of Fig. Q2
d. The engineer made two layout errors. Identify these errors
Fig. Q2 Layout to be submitted
Question 3
Referring to circuit shown in Fig. Q3
a). What type of CMOS circuit is this?
b). What are the advantages of such a circuit?
c). What is the function at node Y?
d) Can you cascade such a block for proper operation? If not what are the remedies that can be adopted?
e) Why do you need to calculate the minimum frequency and how would you calculate it?
d). Derive the maximum operating frequency for the clock signal F. Use Time Constant analysis, and Ri & Cj for the Resistances and Capacitances at different nodes.
( eg. RA for Transistor A and CAD for Capacitance between transistors A & D)
f). Using a similar structure and other blocks needed, construct the transistor diagram of a circuit which can be connected at the output of the circuit of Figure Q3 to generate the function: S = Y + GH + K
Fig. 3 Circuit under investigation
Question 4
The NMOS transistor used in this question has the following model parameters:
VTO = 0.6V, TOX= 100Ao, mo=550cm2/V-sec, g =0.61V1/2, l = 0.033V-1, Fs=-0.6V.
In the circuit of Figure Q4, determine:
1. The threshold voltage of the NMOS transistor.
2. The region of operation of the transistor.
3. The W/L of the transistor.
4. Determine the VOL of the circuit and draw the VTC curve.
Fig. Q4
Question 5.
In 2 or 3 lines Define or Explain the following:
1. What is VDD and Ground bounce?
2. What is Field Oxide used for?
3. What is the difference between the silicon used for transistor gate and the silicon used in the substrate?
4. What is Velocity Saturation?
5. What is Mobility Degradation?
6. What is punch through phenomena?
7. What is surface inversion?
8. What is the difference between Latch and Flip Flop?
9. What is Fringing Capacitance?
10. How the delay of a line is related to its length?
Question 6
An Engineer has to design a multi-stage buffer to connect the output of a standard CMOS inverter to a large external capacitive load of CL=50pF. This inverter is marked with the symbol “1X” in Fig. Q6 has a delay of 2 ns and has the following parameters:
VDD=3.3V VTN=-VTP=0.33V KN=KP=200mA/V2
Wp=2mm Wn=1mm Ln=Lp=0.5mm Cox = 6.66fF/mm2
Cd=4.8Cg
(a) Show that the input capacitance Cg of 1X inverter equals to 10fF.
(b) Find the optimal scaling ratio Sopt of the buffer circuit.
(c) Find the number of stages (N) required for the buffer circuit.
(d) Calculate the total delay tp between points A and C.
(e) Determine the current sinking in CL when point C is at 0.1 V
Fig. Q6
CMOSIS5 Design Kit V2.1
.MODEL CMOSN mos3 type=n
+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1
+VTO=0.6566 DELTA=6.9100E-01 LD=4.7290E-08 KP=1.9647E –04
+UO=546.2 THETA=2.6840E-01 RSH=3.5120E+01 GAMMA=0.5976
+NSUB=1.3920E+17 NFS=5.9090E+11 VMAX=2.0080E+05 +ETA=3.7180E-02
+KAPPA=2.8980E-02 CGDO=3.0515E-10 CGSO=3.0515E-10
+CGBO=4.0239E-10 CJ=5.62E-04 MJ=0.559 CJSW=5.00E-11
+MJSW=0.521 PB=0.99
+XW=4.108E-07
+CAPMOD=bsim XQC=0.5 XPART=0.5
*Weff = Wdrawn - Delta_W
*The suggested Delta_W is 4.1080E-07
.MODEL CMOSP mos3 type=p
+PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1
+VTO=-0.9213 DELTA=2.8750E-01 LD=3.5070E-08 KP=4.8740E-5
+UO=135.5 THETA=1.8070E-01 RSH=1.1000E-01 GAMMA=0.4673
+NSUB=8.5120E+16 NFS=6.5000E+11 VMAX=2.5420E+05 ETA=2.4500E-02
+KAPPA=7.9580E+00 CGDO=2.3933E-10 CGSO=2.3922E-10
+CGBO=3.7579E-10 CJ=9.35E-04 MJ=0.468 CJSW=2.89E-10
MJSW=0.505 PB=0.99
+XW=3.622E-07
+CAPMOD=bsim XQC=0.5 XPART=0.5
*Weff = Wdrawn –Delta_W
*The suggested Delta_W is 3.220E-07
Appendix B
VTC Parameters
Solution of the Exam Final .
Winter 08
Question 1
Q1.a
Q1.b
, Wmin , process smallest width, Pull down has 3 series transistors, then WAn= 3Wmin,n = WBn, WCn, WDn. For pull-up the worst condition is 2 series transistors
{
*Values are multiple of Wmin,n
*Transistors are arranged for better fall time.
.
Q1.c
Input
A=B=C=D=0
Pull down resistance = RC+RD+(RA//RB)
= 2 .5 R
Where R is the resistance of one transistor with W/L = 4
Assuming Vtn=0.6 and the effects of VSB are ignored & VDS is small enough to be ignored,
Pull down resistance
Q1.d
Input
A=B=C=0
D=1
Pull down resistance would be infinity and open circuit to ground.
Question 2
Q2.a
Q2.b
2 / Photolithography step to create thin oxide
3 / Photolithography step to deposit Poly silicon
4 / Photolithography step to diffuse P+ silicon “create Active area”
5 / Photolithography step deposit SiO2
6 / Photolithography step to remove SiO2 where contacts are made “open contact area”
* SiO2 Deposition separate all layers
Q2.c 2 Layers
Q2.d 1) Gate extension for P transistor missing
2) Substrate connection to Vdd should be n+
Question 3
Q3
In the worst case
Worst case is when A=1 D=1 C=1, then
Q3
Or we can use a p-block
Q3
a. This circuit is a Dynamic circuit
b. Has inherent pipelining structure
Area is reduced in comparison to CMOS
Current and power is reduced as no short-circuit current is present
Fast speed
c. Y= when =1 =
d. This circuit cannot be cascaded because the output will trigger the next block discharging output node in wrong time.
To remedy, one can follow the circuit by a static inverter or use a P-N-N-P blocks in cascade or use C2MOS to repeat the blocks.
e. If the frequency is too low, we risk losing the output charge through leakage current.
Vy must not drop below VIL of the next block by the end of evaluation period. In worst case for low frequency Cout=C1+Cdp+Csn, where Cdp and Csn are for all input transistors.
Then Cout(VDD-VIL)=Ileakage x t and Fmin=Ileakage /-Cout(VIL-VDD)
f. Max frequency = F=1/2T where T=max(Tcharge, Teval)
In the worst case, Tcharge=
Question 4
Q4, 1
Q4, 2
Q4, 3
Q4, 4
VOL is obtained when Vg=5V
VOL = 5-(2mA)(300)
= 4.4V
When Vin=0, Transistor is off VOH=5Volt
Question 5
Q5
1) Vdd and Vgnd bounce are transient effects due to L di/dt that occurs on Vdd and ground busses due to heavy supply current in short time.
2) The FOX or field oxide is used to isolate different parts of the IC to prevent them from interacting with each other.
3) The silicon used in the gate is polysilicon and has greater conductance. The substrate is usually intrinsic silicon, a semiconductor.
4) This is a point when increasing the Electric field density has no effect on the speed of the carriers.
5) This is a point when mobility has no longer a linear relationship with the Electric field and velocity.
6) Punch through effect is when the drain voltage is increased to a point that the depletion region extends to near the source (destination) and electrons are injected directly into the source.
7) This is a point when surface charge changes polarity and becomes the same as the source and drain.
8) A latch is level dependant while the Flip-Flop is edge dependant.
9) It is the capacitance due to the edge of the wire to the substrate below an isolation.
10) The delay is related to the square of the length .
Question 6
.
a)
b) Delay
Also , where S is the scaling factor of the tapered buffer, N is the number of stages and Y is the load ratio.
N ln S = ln Y
c)
d) Delay =
=
Buffer A to B
e) Calculating the current sinking into C2
Last Stage
Cout = CL +Cdn,7 + Cdp,7
= CL + 3Cdn
C7 = CL/S=50pF/e (approximate value)
The last stage is can be calculated as follows, assuming the effects of Cdb is negligible and 18.4pF represents the input capacitance of the 7th stage.
Last stage is in Linear Region
Page 17 of 17 COEN 451 Winter 2008