CSE261 FALL 99
CSE261 Design Flow Overview
Procedure to Create a New AHDL Design
•If this is the first design, create new folder: c:\cse261\your_group
–“your_group” is your group’s personal folder
–Invoke “Active-HDL 3.5” (AHDL)
–The previously opened design will be opened
•SelectFile => New Design;
–Click OK to close the current design
•Set location of design folder to c:\cse261\your_group
•Set design name to LABX and click NEXT
–the “default working library” will automatically be set to the name of the design (e.g., LABX).
–If you get a message that a design or library named LABX already exists, then pick a different name (and use this name wherever LABX appears in this procedure!). In general, every design should have a unique name.
We will almost always create new projects based on a standard template project. This is because we are dealing with a fixed hardware platform in which specific signals will always be associated with particular pins on the FPGA. So, when the system asks “How would you like to create new sources?” proceed as follows:
•Select: Create Empty Design
•click NEXT, click FINISH
–the empty design should now have been created
•Leave AHDL running and using the Windows Explorer browse to “c:\cse261ref\”
–the file “lab0.vhd” should be listed as type “Active VHDL Source”
•Select & Copy lab0.vhd
•Browse to “c:\cse261\your_group\labx\src\” and paste lab0.vhd
•Select the file lab0.vhd and rename it to labx.vhd
•Returning to Active HDL, make sure the “Files” tab is active in the “DESIGN BROWSER” window. Double-click on “Add New File”.
•Select “Add Existing File” and click “OK”
•When the “Add Files To Design” window pops up, your copy of lab0.vhd (renamed as labx.vhd) should be visible.
•Select file labx.vhd and click “ADD”
–labx.vhd should now appear in the design hierarchy shown in the DESIGN BROWSER.
•Double-click on file labx.vhd to bring it to the editor window.
•Use Search=> Replace to change all occurrences of “lab0” to “labx” in the file
•Click the Compile icon on the toolbar to compile the file
–the file should compile with 0 errors and several warnings which, for now, we may ignore.
•Exit Active-VHDL
•You have created a new AHDL design that may be subsequently accessed and modified.
Procedure to Create FPGA Express Synthesis Project
•Invoke “FPGA Express” (the train icon)
•Create new FPGA Express project
–File => New
–Browse to c:\cse261\your_group\labx
–Enter a name for the project folder (such as synlabx)
–Click “Create”
•The “Identify Sources” window will activate and the current directory displayed should be c:\cse261\your_group\labx
•Browse to the “src” folder and ensure that “files of type” includes *.vhd files
–labx should be visible (full name labx.vhd)
•Select labx; Click “OPEN”
–You should see a “Design Sources” window which indicates that labx.vhd is now part of the synlabx synthesis project. Note that this is NOT a copy of the file but a path to the file.
•You have just created an FPGA Express project and added a VHDL source file to it. This is typically done once per Active-VHDL (AVHDL) design.
•Exit FPGA Express
•You will typically create one FPGA Express synthesis project for each design. To open an existing synthesis project:
–Invoke FPGA Express
–Browse to your FPGA Express project using File => Open
–Double-click on the project descriptor file which should have the train icon.
Procedure to Synthesize a Design:
•Assuming you have set up an FPGA Express synthesis project with “labx.vhd” as the VHDL source file, synthesizing the design involves the following four steps (using the FPGA Express terminology):
1. “Update” the design: Check source files for VHDL syntax errors and produce intermediate, internal representation of design for the next step
2. “Implement” the design: translate the design to specific target technology primitive functional blocks. In our case, the target technology is always the Xilinx XC4010XL-PC84-3 chip.
3. “Optimize” the design: self explanatory; This is NOT optional.
4. “Export Netlist”: produce an output file which will be input to the Xilinx Implemenation Tools software.
Although the synthesis process is complicated, it is a simple procedure for the user assuming you have provided error free VHDL source and have not violated any design rules not detectable by the VHDL analyzer in Active-VHDL.
•Observe the toolbar on FPGA Express: the items between the “STOP” and “HELP” icons represent the linear sequence of operations necessary to synthesize the design.
–The first, “Add Sources” is typically done once when you create the synthesis project.
–The second, “Update”, must be performed whenever we have made changes to the source code. It is assumed that Active-VHDL has reported zero errors when the modified code was analyzed. We may or may not have actually simulated the design.
–The next item, a drop down list, lets us select the “top level design entity”. For most of our labs this will be trivial since there will be only one entity.
–The next three icons are: Create Implementation, Optimize, and Export Netlist.
The end result of the synthesis process is the exported netlist which would be labx.xnf in our example. An “xnf” file is a Xilinx Netlist Format file. This is a human readable ASCII file which may be viewed with a text editor.
•Here is the step by step synthesis procedure:
–If the source file, labx.vhd, in the design sources window has a “?” over it, you must “update” the file. Select the file and click the Update icon on the tool bar. You can also right-click while the file is selected and a menu will pop up which has “update file” as an option. If the file has no syntax errors (and it shouldn’t since these have presumably been corrected in the AVHDL environment) the “?” will be replaced by a check mark after the update process completes.
–Next, we need to “implement”: click on the “+” next to labx.vhd in the design sources window. Entities within labx.vhd will now be displayed - generally just one for CSE261. Select the labx entity.
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Procedure to Synthesize a Design: (Continued)
–The “create implementation” icon on the tool bar should now be active - click on it. The implementation settings window should appear. Ensure that these settings are as follows:
Name: labx
Vendor: XILINX
Family: XC4000
Device: 4010XLPC84
Speed Grade: XL-3
Optimize Area, Effort Low
Clock Speed: 12MHz
Ensure that “Skip Constraint Entry” and “Do Not Insert I/O Pads” are NOT selected.
Click OK.
–After “Implementation”, there should be a labx “Chip” in the “Chips” window (with a green checkmark on the chip).
–Select the chip and the Optimize icon should activate. Click on it.
–An “optimized” chip should appear in the “Chips” window after the optimization process completes. The “!” indicates that there are warnings. We can ignore them for labx.
–Select the optimized chip and the “Export Netlist” icon becomes active. Click on it.
–Set the destination folder one level up in the labx folder (c:\cse261\your_group\labx)
–You should have now successfully synthesized a netlist (labx.xnf) for the labx design.
Use the explorer to verify that it is actually there and if you wish, view the file with the notepad
(be careful not modify it!).
•When you re-synthesize your design as changes are made to the VHDL source, FPGA Express will add new “chips” to the “Chips” window. To avoid confusion, delete earlier chips.
•When archiving your design, it is generally not necessary (or desirable) to save the synthesis project as it is so easy to simply re-generate it.
Procedure to Produce Downloadable Bitstream:
•If you have not yet created a Xilinx Design Manager Project for your design, do so now:
–Copy the file c:\cse261ref\lab0.ucf to c:\cse261\your_group\labx\labx.ucf. The user constraint file locks the design’s input and output signals to specific pins on the physical FPGA chip.
– Invoke the Xilinx Design Manager.
–Select File => New Project
–Click “Browse” for “Input Design” and browse to “c:\cse261\your_group\labx”.
In the Browse window, make sure that “Files of Type” is set to XNF files. You should see “labx.xnf” in your labx design folder.
–Select labx.xnf; Click Open.
–The default (XILINX) project directory should be “proj” in your labx design directory.
–Add a comment and click OK.
–Select Design => Implement to get to the implementation form.
BE ABSOLUTELY SURE THE PART IS SET TO XC4010XL-3-PC84!
–Click Options.
–In the Control Files section ensure “Guide Design” is “None”
–Select the User Constrain File by browsing to “c:\cse261\your_group\labx” and selecting the previously copied file labx.ucf.
IT IS ABSOLUTELY NECESSESSARY THAT THIS FILE BE SET AS THE CONSTRAINT FILE IF YOU WANT THE DESIGN TO ACTUALLY FUNCTION!
–The Program Options Templates should both be “Default”.
–“Optional Targets” should include only “Produce Configuration Data”.
•Click OK and the Implement window comes up; Click Run to invoke the Flow Engine which controls the sequential execution of the following processing steps: translation, mapping, place and route, and configuration bitstream generation. The time required to complete these processing steps is dependent on the size and complexity of the design. At times, the flow engine may appear to be stalled. Please be patient.
•If all goes well, the Flow Engine completes resulting in the file labx.bit being produced and placed in “c:\cse261\your_group\labx”.
•Invoke a DOS window and change to your design directory “c:\cse261\your_group\labx”.
•Run the command “xsload labx” to download the labx.bit file to the FPGA.
–Ensure that the parallel cable and power supply cable are connected to the XS-40 board.
–The xsload.exe program has no feedback from the board to detect that the load was successful. Therefore, if there is an error (such as no power) it will not be detected.
•The LABX circuit should cause the XS-40 board’s seven segment LED to count from 0 to 9 repetitively at approximately 1Hz rate.