1.  Course Description/Goals

Course Description

CMP 334: Computer Organization. 4 hours, 4 credits.
Introduction to digital logic-expressions, gates, flip-flops, adders, buses, multiplexers. Introduction to assembly language and assembly level organization - data representation, instruction formats, addressing modes, interrupts. Memory systems - caches (mapping and management policies) and memory hierarchies, latency and bandwidth, virtual memory (page tables, TLB). Input/Output- buses, channels and DMA. Performance consideration,pipe-lining, RISC architecture, branch prediction, introduction to instruction level parallelism.
PREREQ: CMP 230 and CMP 232 or departmental permission.

2.  Instructor Information

Anthony Cocchi

Phone: 718-960-5866 Office Hours: 3-3:30 pm. T/Th, GI 137A

Bowen Alpern

Office Hours: 4-5:30 pm. T/Th GI 137A

3.  Course Learning Objectives (revised 8/2012)

At the end of this course students will be able to:- Understand how basic processor components such as Flip/Flops, registers,buses, adders, clocks, and control logic are built from digital logic.

- Do a comparison of instruction sets and the architectures of RISC computers, CISC and Stack based machines.

- Understand computer pipe-lining including the performance benefits and hazards; and the hardware and software techniques used to minimize the negative impacts of the hazards.

- Use Amdahl's law and the computer performance equation to predict the impact of changes to hardware configurations such as faster clocks, better Floating point units etc.

- Understand the memory hierarchy and the impact of various cache organizations. Be able to predict the performance of memory hierarchy changes.

- Understand the implications of todays muti-core processor chips including synchronization and memory consistency

- Predict performance of disk drives and the benefits and costs of the various RAID configurations

4.  Required textbook and materials

Computer Organization and Design: The hardware/software interface version: ARM edition ISBN 978-0-12-801733-3 (or earlier edition) Authors: Hennessy and Patterson:

Other textbooks -Computer Organization and Architecture - Null and Lobur -Computer Organization and Architecture - Stallings

5.  Grading Policy

Exam 1 20%

Exam 2 20%

Final 40%

Homework 20%

6.  Accommodating Disabilities

Lehman College is committed to providing access to all programs and curricula to all students. Students with disabilities who may need classroom accommodations are encouraged to register with the Office of Student Disability Services. For more information please contact the Office of Student Disability Services, Shuster Hall, Room 238, phone number, 718-960-8441.

7.  Other Items

Schedule (ARM edition of textbook)

Introduction ----- 1 week

Logic Design Appendix A (A.1-A.9, A.11) 2 weeks

Instruction Set Chapter 2 (2.1-2.7) 2 weeks

Computer Arithmetic (optional) Chapter 3 (3.1-3.3, 3.5) 1 week

The Processor Chapter 4 (4.1-4.9) 2 week

Exploiting Memory Hierarchy Chapter 5 (5.1-5.4, 5.7, 5.10) 2 week

Multiprocessors and Clusters Chapter 6 (6.1-6.3, 6.7, 6.8) 1.5 week

Disk IO and IO (5.11) 1 weeks

Computer Performance(optional) . 5 week

Online material http://booksite.elsevier.com/9780128017333/

http://Textbooks.elsevier.com/9780124077263

Times are approximate

·  There is an attendance requirement at Lehman College. Students with poor attendance and repeated lateness (no matter what the reason) will have their grades reduced.

·  If an emergency prevents you from attending class, it is your responsibility to obtain notes from a classmate and study them for understanding. It is a wise move to get a buddy.