Computer Applications and Management

Computer Applications and Management

A-4, Paschim Vihar, New Delhi-63.

MCA – 2nd Semester (2010-13)

Ist Internal Test Computer Organization – MCA - 107

Max. Marks: 45 Max. Time: 02 Hrs.

Note: Attempt any four of the following from Section A and B. Marks are indicated against each question

SECTION-A

Q1. Answer any ten of the following: (1.5*10=15)

i.  What is the difference between computer organization and computer architecture?

ii.  Show the hardwire, including logic gates for the control function that implements the statement.

T8: if (c=0) then

iii.  List the micro-operation that transfer bit 1-8 of register A to bits 9-16 of register B and bits 1-8 of register B to bits 9-16 of register A. Draw a block diagram of the hardware required.

iv.  A digital system has 16 registers, each with 32-bits to provide parallel data transfer from each register to every other register. How many lines are needed if the for direct transfer and how many lines are needed if the transfer is through a common bus.?

v.  A control memory of 1024 words of 32 bits each. The microinstruction has three fields the micro-operations field has 16 bits.

vi.  Draw a block diagram of a bus system connected between four register A, B, C and D, so that information can be transferred from one register to any other register. Use necessary hardware to design.

vii.  Consider two 8-bit numbers in ALU, A=01000011 and B=10000110, perform the operations of add and subtract and determine the values of status bits C, S, Z, V.

viii.  A processor has 16 registers, an ALU with 16 logic and arithmetic functions and a shifter with 8 operations, all connected by an internal processor. Design a micro-instruction format to specify the various micro-operations for the processor.

ix.  A micropprogrammed CPU has 1 K words in control memory. Each instruction needs 8 microinstructions. Assuming that the opcode in the macroinstruction is of 5 bits length, propose a mapping scheme to generate control memory address for the opcode.

x.  The microprogrammed control has propagation delay times 40ns to generate the next address, 10ns to transfer the address into control address register, 40 ns to access the control memory ROM, 10 ns to transfer the microinstruction into the control data register and 40 ns to perform the required micro-operation specified by the control word. What is the maximum clock frequency the control can use?

xi.  An encoded microinstruction format is to be used .Show how a 10 bit microinstruction field can be divided into subfields to specify 94 different actions.

SECTION-B

Any any two parts from each question.

Q1. a) Draw the logic diagram of a 2-to-4 decoder with only NOR gates include an enable

input (5) (2.5)

b) Show that a JK flip flop can be converted cab be converted to a D flip flop with an (5)

inverter between J and K inputs.

c) Design bi-directional shift register with parallel load. (5)

Q2. a)

(i) An 8-bit register contains the binary value of Decimal 40.What is the register value

after arithmetic shift right and shift left? Staring from, determine the register value after

arithmetic shift left, and state whether there is an overflow. (3)

(ii) Design a 4 bit decrementer circuit using full adders. (2)

b)  Design a typical stage to implement the following micro-operations

(5)

c) A computer similar to the basic computer has six timing signals and only one flip –

flop F for cycle control. When F=0 control performs the fetch and indirect cycle (if

necessary)? When F=1 it executes the instruction? List the control functions and micro- operation for the computer when F=0. (5)

Q3. a) Write the symbolic micro-program for Store also include the required micro-program (5)

b) Draw the flowchart for Interrupt Cycle (5)

c) Assume that the input logic of the micro program sequencer has four inputs I2, I1,

I0 , T(test) and three outputs , S1,S0, and L. The operations that are performed in

the unit are listed in the following table. Design the input logic circuit using minimum number of gates. (5)

I2 / I1 / I0 / Operation
0 / 0 / 0 / Increment CAR if T=1,jump to AD if T=0
* / 0 / 1 / Jump to AD unconditionally
1 / 0 / 0 / Increment CAR unconditionally
0 / 1 / 0 / Jump to AD if T=1, increment CAR if t=0
1 / 1 / 0 / Call subroutine if T=1,increment CAR if T=0
0 / 1 / 1 / Return from subroutine unconditionally
1 / 1 / 1 / Map external address unconditionally