Brief Description of the L1MU Mtcxx Trigger Algorithms

Brief Description of the L1MU MTCxx Trigger Algorithms

1.Introduction

The trigger information flow in the L1MU system is to form octant trigger decisions which are used to form regional trigger decisions which are used to form the L1MU specific trigger decisions. The octant trigger decisions are made on the Muon Trigger (MTCxx) cards. On each MTCxx card is a Muon Trigger Flavor Board (MTFB) that contains the octant trigger decision algorithm. The algorithms are implemented in FPGA's on the MTFB's. There are four types of MTFB's as shown in Table 1.

Type / Description
CF MTC05 / Use L1CFT tracks and APHI/CS scintillator hits
CF MTC10 / Use PDT wire hits and APHI/CS scintillator hits
EF MTC05 / Use L1CFT tracks and PIXEL scintillator hits
EF MTC10 / Use MDT wire centroids and PIXEL scintillator hits

Table 11 Types of MTFB's containing octant trigger algorithms used on the MTCxx cards.

For each type of MTFB we specify the inputs and outputs, and describe the algorithm.

2.CF MTC05

The inputs to the CF MTC05 cards in Octant 1 are given in Table 2.1.

MTCxx Inputs / Description
L1CFT tracks / 6 highest PT tracks from L1CFT
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
APHI A-Layer hits / 48 A-Layer PIXEL hits from SFE
APHI A-Layer hits
CS C-Layer hits / 96 C-Layer CS hits from MCON
Not used

Table 21 Inputs to the CF MTC05 card for octant 1.

The outputs from the CF MTC05 card are given in Table 2.2

Description / Name
2-bit counter, APHI or CS, PT1, + / PT1 Scint Loose for 0.0 < || < 1.0
2-bit counter, APHI or CS, PT1, -
2-bit counter, APHI or CS, PT2, + / PT2 Scint Loose for 0.0 < || < 1.0
2-bit counter, APHI or CS, PT2, -
2-bit counter, APHI or CS, PT3 / PT3 Scint Loose for 0.0 < || < 1.0
2-bit counter, APHI or CS, PT4 / PT4 Scint Loose for 0.0 < || < 1.0
2-bit counter, APHI and CS, PT2 / PT2 Scint Tight for 0.0 < || < 1.0
2-bit counter, APHI and CS, PT3 / PT3 Scint Tight for 0.0 < || < 1.0
2-bit counter, APHI and CS, PT4 / PT4 Scint Tight for 0.0 < || < 1.0
Spare
Spare
Spare
Spare
Spare

Table 22 Outputs from the CF MTC05 card for octant 1

The CF MTC05 algorithm is as follows. A schematic representation is given in Figure 2.1. APHI and CS hits from the A- and C-layers are first demultiplexed. Next, combinations (correlations) of APHI/CS hits are found for each of ten phi slices in the octant. Though reported in phi, the correlations use both phi and etainformation. Only one combination is possible on the CF MTC05: AC. This combination is found separately for PT differential thresholds PT2-PT4. Hits in ten phi slices are also reported separately for the APHI and CS layers. The various combinations are output to the next logic stage using ten bits per combination. The ten bits correspond to phi wedges, centered on the APHI counters. Two-bit sums of APHI and CS counters are also formed in this initial stage. Two FPGA's are used to form the above combinations, with differential PT1 and PT2 combinations found on one FPGA and differential PT3 and PT4 combinations found on the other.

Concurrently with the above logic, one FPGA is used to decode and process the track information from the L1CFT trigger. ACENT, Track Found, and Sign information for each of twelve L1CFT phi sectors are input to the FPGA. This information is used to produce two sign times twelve phi bits for each of four differential PT bins. A "1" indicates a good track with the appropriate sign and PT was found by the L1CFT trigger in that L1CFT phi sector. Tracks from the twelve L1CFT phi sectors are processed simultaneously and up to six tracks per phi sector are processed within one bunch crossing.

Outputs from the above three FPGA's are sent to four FPGA's that comprise the next logic stage. Each of the four FPGA's corresponds approximately to one of the four differential PT bins though some PT2 terms are formed on the PT1 FPGA. The differential PT1-PT4 bins are approximately 2 < PT < 4 GeV/c, 2 < PT < 7 GeV/c, 7 < PT < 11 GeV/c, and 11 GeV/c < PT. In these four FPGA's the A, C, and AC combinations described above are matched with the appropriate L1CFT tracks.

The inputs to each of the four FPGA's are two sign times twelve bits corresponding to which of the L1CFT phi sectors contained a good track. Also input are the twelve phi sectors times six bits of HCENT information corresponding to each L1CFT track. Note that up to six sets (tracks) worth of the above information is sent for each of the twelve L1CFT phi sectors within 132ns. Also sent to the FPGA's are the A, C, and AC combinations for that differential PT threshold described above. In these FPGA's, the L1CFT phi sector and HCENT information are used to form ten new phi wedges that will match the APHI/CS phi wedges described above. Next matches are made between the ten bits of these new phi wedges and the ten bits of each of the APHI/CS combinations above.

The outputs of the four FPGA's are two-bit counters giving the number of matched L1CFT-APHI/CS combinations. For example, for differential threshold PT3, the outputs are two-bit counters for A, A or C, and AC. For differential threshold PT1, there are only two two-bit counters corresponding to A+ and A- where the + and - describe the sign of the L1CFT track.

Also, in addition to the above two-bit counters, ten bits of APHI phi slice information is passed to the summing FPGA.

In the final stage of logic, the two-bit counters for the octant trigger decisions listed in Table 2.2 are formed. One FPGA is used for this final stage of logic.

3.CF MTC10

The inputs to the CF MTC10 cards in Octant 1 are given in Table 3.1.

MTCxx Inputs / Description
PDT A-Layer hits / 96 A-Layer hits from CB
PDT A-Layer hits
PDT A-Layer hits
PDT B-Layer hits
PDT B-Layer hits / 96 B-Layer hits from CB
PDT B-Layer hits
PDT B-Layer hits
PDT B-Layer hits
PDT C-Layer hits / 96 C-Layer hits from CB
PDT C-Layer hits
PDT C-Layer hits
PDT C-Layer hits
PDT C-Layer hits
APHI A-Layer hits / 48 A-Layer APHI hits from SFE
APHI A-Layer hits
CS C-Layer hits / 96 C-Layer CS hits from MCON

Table 31 Inputs to the CF MTC10 card for octant 1.

The outputs from the CF MTC10 card are given in Table 3.2

Description / Name
2-bit counter, A or B or C PDT centroid / Wire Loose for 0.0 < || < 1.0
2-bit counter, AB or AC PDT centroid / Wire Tight for 0.0 < || < 1.0
Spare
Spare

Table 32 Outputs from the CF MTC10 card for octant 1

The CF MTC10 algorithm is as follows. A schematic representation is given in Figure 3.1. PDT hit and APHI/CS hit data are first demultiplexed. Next, logic is performed that confirms each PDT hit as having a corresponding APHI or CS hit. For the B-layer, CS hits are used as confirmation. Confirmed hits are subsequently used to form PDT centroids with half-cell resolution in each of layers. The PDT centroids are then multiplexed before being sent to the next logic stage. Two-bit counting of the number of APHI and CS counters is also performed. One FPGA is used for each of the A-, B-, and C-layers.

In the next stage of logic the centroids are first demultiplexed. Next AB, AC, and BC combinations (correlations) corresponding to real tracks passing through those layers are found. Ideally, AxB, ABx, AxC, and BxC combinations are found where the x signfies the layer which is the anchor. These combinations would allow us to later form "AB and AC" combinations if needed. Two-bit counters from the various combinations are formed before being sent to the next logic stage. Examples of the combinations are "A or B or C" and "AB or AC". Some additional logic is used to reduce the number of "twos". One FPGA is used for each third of the centroids (.3A, .3B, .3C).

In the final stage of logic, the two-bit counters for the octant trigger decisions listed in Table 3.2 are formed. One FPGA is used for this final stage of logic. . Note that many other combinations other than those listed in Table 3.2 are possible should looser or tighter octant trigger decisions be needed.

4.EF MTC05

The inputs to the EF MTC05 cards in Octant 1 are given in Table 4.1.

MTCxx Inputs / Description
L1CFT tracks / 6 highest PT tracks from L1CFT
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
L1CFT tracks
PIXEL A-Layer hits / 48 A-Layer PIXEL hits from SFE
PIXEL A-Layer hits
PIXEL B-Layer hits / 96 B-Layer PIXEL hits from MCON
PIXEL C-Layer hits / 96 C-Layer PIXEL hits from MCON

Table 41 Inputs to the EF MTC05 card for octant 1.

The outputs from the EF MTC05 card are given in Table 4.2

Description / Name
2-bit counter, A or B PIXEL, PT1, + / PT1 Scint Loose for 1.0 < || < 1.5
2-bit counter, A or B PIXEL, PT1, -
2-bit counter, A or B PIXEL, PT2, + / PT1 Scint Loose for 1.0 < || < 1.5
2-bit counter, A or B PIXEL, PT2, -
2-bit counter, A or B PIXEL, PT3 / PT3 Scint Loose for 1.0 < || < 1.5
2-bit counter, A or B PIXEL, PT4 / PT4 Scint Loose for 1.0 < || < 1.5
2-bit counter AB or BC PIXEL PT2 / PT2 Scint Tight for 1.0 < || < 1.5
2-bit counter AB or BC PIXEL PT3 / PT3 Scint Tight for 1.0 < || < 1.5
2-bit counter AB or BC PIXEL PT4 / PT4 Scint Tight for 1.0 < || < 1.5
2-bit counter, A or B PIXEL / Scint Loose for 1.5 < || < 2.0
2-bit counter, AB or BC PIXEL / Scint Tight for 1.5 < || < 2.0
Spare
Spare
Spare

Table 42 Outputs from the EF MTC05 card for octant 1. PT1, PT2, PT3, PT4 are for PT > threshold 1, etc. They are integrated, not differential, PT ranges.

The EF MTC05 algorithm is as follows. A schematic representation is given in Figure 4.1. PIXEL hits from the A-, B-, and C-layers are first demultiplexed. Next, combinations (correlations) of PIXEL hits are found for each of ten phi slices in the octant. Though reported in phi, the correlations use both phi and etainformation. The combinations are AxB, ABx, AxC, and BxC where the x refers to the anchoring layer. These combinations are found separately for PT differential thresholds PT2-PT4. Hits in ten phi slices are also reported separately for the A-, B-, and C-layers. Combinations are found for both 1.0 < || < 1.5 and 1.5 < || < 2.0 regions, where the boundary is defined by a set PIXEL counter row number. The various combinations are output to the next logic stage using ten bits per combination. The ten bits correspond to phi wedges, usually centered on the A-layer PIXEL counters. Two-bit sums of A-, B-, and C-layer PIXEL counters are also formed in this initial stage. Two FPGA's are used to form the above combinations, with differential PT1 and PT2 combinations found on one FPGA and differential PT3 and PT4 combinations found on the other. A detail is that for the region 1.5 < || < 2.0, what is reported are not ten-bit phi wedges but rather two-bit sums of the combinations A, A or B, AB or BC, AB or BC or AC, and ABx and BxC.

Outputs from the above three FPGA's are sent to four FPGA's that comprise the next logic stage. Each of the four FPGA's corresponds approximately to one of the four differential PT bins though some PT2 terms are formed on the PT1 FPGA. The differential PT1-PT4 bins are approximately 2 < PT < 4 GeV/c, 2 < PT < 7 GeV/c, 7 < PT < 11 GeV/c, and 11 GeV/c < PT. In these four FPGA's the PIXEL and individual layer combinations described above are matched with the appropriate L1CFT tracks.

The inputs to each of the four FPGA's are two sign times twelve bits corresponding to which of the L1CFT phi sectors contained a good track. Also input are the twelve phi sectors times six bits of HCENT information corresponding to each L1CFT track. Note that up to six sets (tracks) worth of the above information is sent for each of the twelve L1CFT phi sectors within 132ns. Also sent to the FPGA's are the various PIXEL combinations for that differential PT threshold described above. In these FPGA's, the L1CFT phi sector and HCENT information are used to form ten new phi wedges that will match the PIXEL phi wedges described above. Next matches are made between the ten bits of these new phi wedges and the ten bits of each of the PIXEL combinations above.

The outputs of the four FPGA's are two-bit counters giving the number of matched L1CFT-PIXEL combinations. For example, for differential threshold PT3, the outputs are two-bit counters for A, A or B, A or B or C, AB, AB or BC, AB or BC or AC, and ABx and BxC. For differential threshold PT1, there are only two two-bit counters corresponding to A+ and A- where the + and - describe the sign of the L1CFT track.

Also, in addition to the above two-bit counters, ten bits of A-layer PIXEL phi slice information is passed to the summing FPGA.

In the final stage of logic, the two-bit counters for the octant trigger decisions listed in Table 4.2 are formed. Note that the two-bit sums output are for integrated PT thresholds PT1-PT4. One FPGA is used for this final stage of logic. Note that many other combinations other than those listed in Table 4.2 are possible should looser or tighter octant trigger decisions be needed.

5.EF MTC10

The inputs to the EF MTC10 cards in Octant 1 are given in Table 5.1.

MTCxx Inputs / Description
MDT A-Layer centroids / 96 A-Layer centroids from MCEN
MDT A-Layer centroids
MDT A-Layer centroids
MDT A-Layer centroids
MDT B-Layer centroids / 96 B-Layer centroids from MCEN
MDT B-Layer centroids
MDT B-Layer centroids
MDT B-Layer centroids
MDT C-Layer centroids / 96 C-Layer centroids from MCEN
MDT C-Layer centroids
MDT C-Layer centroids
MDT C-Layer centroids
PIXEL A-Layer hits / 48 A-Layer PIXEL hits from SFE
PIXEL A-Layer hits
PIXEL B-Layer hits / 96 B-Layer PIXEL hits from MCON
PIXEL C-Layer hits / 96 C-Layer PIXEL hits from MCON

Table 51 Inputs to the EF MTC10 card for octant 1.

The outputs from the EF MTC10 card are given in Table 5.2

Description / Name
2-bit counter, A or B MDT centroid / Wire Loose for 1.0 < || < 1.5
2-bit counter, AB or BC MDT centroid / Wire Tight for 1.0 < || < 1.5
2-bit counter, A or B MDT centroid / Wire Loose for 1.5 < || < 2.0
2-bit counter, AB or BC MDT centroid / Wire Tight for 1.5 < || < 2.0

Table 52 Outputs from the EF MTC10 card for octant 1.

The EF MTC10 algorithm is as follows. A schematic representation is given in Figure 5.1. MDT centroid and PIXEL hit data are first demultiplexed. Next the MDT centroids are or'ed by 2 or possibly, 4. Logic is next performed that confirms each MDT centroid as having a corresponding PIXEL hit in the same layer. The confirmed MDT centroids are then multiplexed before being sent to the next logic stage. Two-bit counting of the number of A-, B-, and C-layer PIXEL counters is also performed. One FPGA is used for each of the A-, B-, and C-layers. The boundary at || =1.5 is defined by a set PIXEL counter row number.

In the next stage of logic the centroids are first demultiplexed. Next AB, AC, and BC combinations (correlations) corresponding to real tracks passing through those layers are found. Ideally, AxB, ABx, AxC, and BxC combinations are found where the x signfies which layer is the anchor. These combinations would allow us to later form "AB and AC" combinations if needed. Two-bit counters for the various are formed before being sent to the next logic stage. Examples of the combinations are "A or B or C" and "AB or AC". Some additional logic is used to reduce the number of "twos". One FPGA is used for each third of the centroids (.3A, .3B, .3C).

In the final stage of logic, the two-bit counters for the octant trigger decisions listed in Table 5.2 are formed. One FPGA is used for this final stage of logic. . Note that many other combinations other than those listed in Table 5.2 are possible should looser or tighter octant trigger decisions be needed.