# Boolean Algebra and Logic Gates8

DOC/LP/01/28.01.09

/ LESSON PLAN / LP-CS2202
LP Rev. No: 01
Date: 25.6.2012
Page 01 of 06
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN
Unit: I Branch: IT Semester: III

Unit syllabus:

BOOLEAN ALGEBRA AND LOGIC GATES8

Review of binary number systems - Binary arithmetic – Binary codes – Boolean algebra and theorems - Boolean functions – Simplifications of Boolean functions using Karnaugh map and tabulation methods – Logic gates

Objective:

This unit discusses different methods used for the simplification of Boolean functions. It also gives a detailed idea of number system and binary arithmetic.

Session
No / Topics to be covered / Time / Ref / Teaching Method
1 /

## Introduction to Number System

/ 50m / 1(pp1-7)
2(7-10) / BB
2 / Conversion of number system from one radix to another in detail / 50m / 1( 5-12) / BB
3 / Binary Arithmetic
Binary addition, Binary Subtraction, Binary Multiplication, BCD, ASCII, GRAY CODE and Error correcting codes / 50m / 1(13-27)
2(10-15) / BB
4 / Boolean algebra and theorems / 50m / 1(33-37)
2(17-57) / BB
5 /

## Boolean Functions and Representing Boolean Functions

Simplification of Boolean functions using theorems. / 50m / 1(40-59)
2(58-70)
Internet / BB
6 /

## Introduction to map method, two, three variable k-maps

/ 50m / 1(64-70) / BB
7 /

## Four and five variable maps, simplification of Boolean functions using K-map

/ 50m / 1(70-76) / BB
8 /

## K-map using don’t care conditions

Simplification of Boolean functions using don’t care conditions / 50m / 1(80-82) / BB
9 /

Simplifications of Boolean functions using tabulation method

/ 50m / 2(149-167) / BB
10 /

Introduction to logic gates

/ 50m / 1(51-59)
2(101-113) / BB
11 /

Problems in K- map method

/ 50m / Tutorial sheet / BB
12 /

Problems in Tabulation method

/ 50m / Tutorial sheet / BB
/ LESSON PLAN / LP-CS2202
LP Rev. No: 01
Date: 25.06.2012
Page 02 of 06
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN
Unit: II Branch: IT Semester: III

Unit syllabus:

COMBINATIONAL LOGIC9

Combinational circuits – Analysis and design procedures - Circuits for arithmetic operations - Code conversion – Introduction to Hardware Description Language (HDL)

Objective:

This unit provides the overview of combinational logic, by discussing various topics related to combinational circuits and code conversion.

Session
No / Topics to be covered / Time / Ref / Teaching Method
13 /

Introduction to Combinational Logic

Analysis and design procedures for combinational circuits. / 50m / 1(111-115) / BB
14 / Design of Combinational circuit for a given Boolean function.
Discussion with various examples / 50m / 1(115-118) / BB
15 / Design of Combinational circuits for arithmetic operations
16 / carry propagation, binary subtractor, overflow / 50m / 1(123-129) / BB
17 / Decimal adder, binary multiplier, magnitude comparator / 50m / 1(129-133) / BB
18 / Code conversion
Definiton, code conversions example, gray code to binary conversion. / 50m / 1(116-118) / BB
19 / Introduction to HDL
Module representation, Gate delays / 50m / 1(147-167)
4(79-88) / BB
20 / Boolean expressions, User defined primitives / 50m / 1(147-167) / BB
21 / Problems in code conversion / 50m / BB
22 / Tutorial / 50m / Tutorial sheet / BB
Continuous Assessment Test – I / 75m
/ LESSON PLAN / LP-CS2202

### LP Rev. No: 01

Date: 25.6.2012
Page 03 of 06
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN
Unit: III Branch: IT Semester: III

Unit syllabus:

DESIGN WITH MSI DEVICES8

Decoders and encoders - Multiplexers and demultiplexers - Memory and programmable logic - HDL for combinational circuits.

Objective:

This unit focuses on advanced concepts of system design like decoders, encoders, multiplexers, demultiplexers and programmable logic.

Session
No / Topics to be covered / Time / Ref / Teaching Method
23 /

Introduction to MSI

Designing of decoders and encoders / 50m / 1(134-139) / BB
24 /

Design of 8x1 decoders and encoders using 4x1 encoders

/ 50m / 1(134-139)
2(227-229) / BB
25 / Introduction to multiplexers.
Designing of multiplexers for various Boolean functions / 50m / 1(141-147)
2(223-226) / BB
26 / Introduction to demultiplexers.
Designing of demultiplexers for various Boolean functions / 50m / 1(141-147)
2(223-226) / BB
27 / Design of 8x1 multiplexer and demultiplexers using 4x1 mux / 50m / 1(141-147) / BB
28 / Memory
RAM, types of memories, memory decoding, Error detection and correction, ROM., Types of ROM. / 50m / 1(255-276) / BB
29 / Programmable logic
Programmable array logic(PAL), Programmable Logic array(PLA). / 50m / 1(276-283) / BB
30 / HDL for combinational circuits.
Gate level modeling, data flow modeling, behavioral modeling / 50m / 1(190-198)
4(89-105) / BB
31 / Problems in Multiplexer and Demultiplexer / 50m / Tutorial sheet / BB
32 / Problems in ROM,PLA,PLA / 50m / Tutorial sheet / BB
/ LESSON PLAN / LP-CS2202
LP Rev. No: 01
Date: 25.06.2012
Page 04 of 06
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN
Unit: IV Branch: IT Semester: III

Unit syllabus:

##### SYNCHRONOUS SEQUENTIAL LOGIC10

Sequential circuits – Flip flops – Analysis and design procedures - State reduction and state assignment - Shift registers – Counters - HDL for sequential logic circuits, Shift registers and counters.

Objective:

To Learn about sequential circuits, counters, shift registers, and state diagrams

Session
No / Topics to be covered / Time / Ref / Teaching Method
33 /

Sequential circuits

Introduction and definitions, Introduction to flip flops, Discussion of SR / 50m / 1(167-172)
3(314-317) / BB
34 / Discussion of D,T, JK flip flops / 50m / 1(167-172)
3(317-328) / BB
35 / Analysis and design procedures
clocked sequential circuits, state equation, state table, state diagram, flip flop input equations. / 50m / 1(180-190)
2(323-345) / BB
36 / State reduction and state assignment / 50m / 1(198-202) / BB
37 / Design of Shift registers using flip flops
Serial transfer, serial addition, universal shift register / 50m / 1(217-227) / OHP
38 / Counters
Design of Ripple counters. / 50m / 1(227-243)
3(337-340) / BB
39 / Design of synchronous counters / 50m / 1(227-243)
3(341-352) / BB
40 / Design of Ring and Johnson counters / 50m / 1(227-243) / BB
41 / HDL for registers and counters / 50m / 1(244-255)
4(97-105) / BB
42 / Problems in Synchronous Sequential Circuits / 50m / Tutorial sheet / BB
43 / Conversion of one flip and another flops and Tutorial / 50m / Tutorial sheet / BB
Continuous Assignment Test II / 75m
/ LESSON PLAN / LP-CS2202

### LP Rev. No: 01

Date: 25.06.2012
Page 05 of 06
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN
Unit: V Branch: IT Semester: III

Unit syllabus:

ASYNCHRONOUS SEQUENTIAL LOGIC10

Analysis and design of asynchronous sequential circuits - Reduction of state and flow tables – Race-free state assignment – Hazards-ASM Chart.

Objective:

This unit deals with analysis and design procedures of asynchronous logic circuits and hazards.

Session
No / Topics to be covered / Time / Ref / Teaching Method
44 /

Asynchronous Sequential circuits

Introduction and discussion of Sequential circuits / 50m / 1(342-344)
2(590-594) / BB
45 / Analysis procedure of asynchronous sequential circuits-Transition table, Flow table / 50m / 1(344-352) / BB
46 / Design procedure of asynchronous sequential circuits-Primitive flow table, reduction of Primitive flow table / 50m / 1(360-367)
2(608-619) / BB
47 /

Reduction of state and flow tables

Implication table / 50m / 1(367-373) / BB
48 /

Merging of flow table, Compatible pairs.

/ 50m / 1(374-379) / BB
49 / Race-free state assignment-Three-row flow-table,four-row flow-table and multiple row method. / 50m / 1(374-379)
3(520) / BB
50 / Hazards-Hazards in combinational logic circuits / 50m / 1(379-384)
2(657-673) / BB
51 /

Sequential circuits, Essential hazards.

/ 50m / 1(379-384) / BB
52 /

Design example for asynchronous sequential circuit-ASM Chart

/ 50m / 1(299-309) / BB
53 /

Problems in Asynchronous Sequential circuits

/ 50m / Tutorial sheet / BB
54 /

Problems in Hazards

/ 50m / Tutorial sheet / BB
Continuous Assessment Test – III
/ 75m
/ LESSON PLAN / LP-CS2202
LP Rev. No: 01
Date: 25.6.2012
Page 06 of 06
Sub Code & Name : CS2202
DIGITAL PRINCIPLES AND SYSTEM DESIGN
Branch: IT Semester: III

Course Delivery Plan:

Week / 1 / 2 / 3 / 4 / 5 / 6 / 7 / 8 / 9 / 10 / 11 / 12 / 13 / 14 / 15
I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II / I II
Units / 1 / / / 2 / / 3 / / 4 / / 5 /

CAT-I CAT-II CAT-III

Books Referred:

TEXT BOOKS:

1. M.Morris Mano, “Digital Design”, 3rd edition, Pearson Education, 2002.

REFERENCES

2. Charles H.Roth, Jr. “Fundamentals of Logic Design”, 4th Edition, Jaico

Publishing House, 2000.

3. Donald D.Givone, “Digital Principles and Design”, Tata McGraw-Hill, 2003.

4. Bhaskar, Jayaram, “A VHDL Primer, 2nd Edition

Prepared by / Approved by
Signature
Name /
###### Ms.G P Bharathi
/ Dr.T.K.Thivakaran
Designation / Asso.Professor &
Asst.Professor / HOD-CSE
Date / 25.6.2012 / 25.6.2012