1.0 Introduction:

Given any VLSI circuit, be it analog or digital, various parameters affect the design and functioning of a circuit. A standard scaling mechanism that is indicative of the efficiency of all the defined parameters is highly desired. The first part of my work is the identification of parameters to be taken into consideration for electromigration, broadly identified as speed, wire levels, interconnects, technology involved, amplification stages, chip size and power utilization in no particular order. The second part involved the failure analysis of circuit interconnects particularly those caused by electromigration. Of the several methods available for such analysis, MTTF was found to be most suitable because of its relative simplicity, effectiveness and wide usage in the industry. In this project, I have implemented a prototype for MTTF estimation for a latch-comparator circuit that I designed.

Of the above-mentioned parameters, the more important are those that can be manipulated at the behest of either the designer or the fabricator while actually designing the circuit. Factors such as the technology used or the chip size take secondary importance because of the following two reasons. Firstly, manufacturers use the same technology for almost all of their designs with similar applications. This seldom varies until the advent of a new generation technology, which makes a substantial difference either in cost or performance. Secondly, the designer is bound to optimize the chip size or the circuit size since all circuits/chips performing the same function are likely to be similar irrespective of the manufacturer. The subtle differences that make his circuit better than that of the next competitor lie in the design itself and/or in the other parameters listed above.

1.1 Approach:

A qualitative analysis of better design practices especially in the case of interconnects and power requirement/usage.

  1. Carry out a component specific analysis and identify materials which, when used in the circuit, enhance the performance Usually each manufacturer typically uses one kind of material for a specific component, depending on parametric considerations.
  2. Implement an analysis method such as the Mean Time to Failure method for interconnects at various nodes. This gives an estimate of a circuit’s life expectancy using circuit specific parameters such as current density, temperature and material of the interconnect.

2.0 Parametric Considerations

2.1 Power:

In any circuit, the time varying circuit current and the parasitics associated with the power distribution network cause a reduction in the time varying voltage drop at the power bus contact or a surge at the ground bus contact. This sudden variation in the voltage has a negative impact on the reliability of the circuit in two possible ways.

The more apparent and less deadly consequence is that the circuit may stop functioning due to a blowout of a particular component or a node. Alternately, any variation in critical voltage levels might lead to alterations in the clocking period - typically as delays. This is observed more in digital circuits that in analog circuits. In addition, even a small variation in circuit parameters might reflect as a substantial change because of the miniature scaling of the circuit. It is desirable to account for this uncertainty.

2.2 Power Grid Optimization

There are two suggested methods for power grid optimization depending on the magnitude of parametric variations. Typically, for small changes, the sensitivity vector of the voltage drop on one node with respect to a small change in the decoupling capacitance at all nodes in the power bus is used to model the variations.

For large variations however, voltage drop variations of all the violator nodes is modeled if one/more decoupling capacitances are charged arbitrarily. [2]

2.3 Typical trade-off problems

Though it is desirable that the operational speed be as high as possible, the chip/circuit size be as compact as can be obtained, the power consumption be kept to a minimum and the wire levels be well-graded, the causes and the desired effects are not as easy to control. This is because the components and the circuit are not totally devoid of any reaction to external fields. Parametric variation demands some kind of trade off between the desired effects such as the speed and the chip size.

For instance, if the integration density (ID), which is indicative of the compactness of the chip/circuit is increased, it is required that the interconnect pitch be increased. An increase in the interconnect pitch results in the increase of parasitic resistances and capacitances. This increase results in a decrease in the operational speed of the circuit. Thus it is necessary to reach a justifiable and common sense trade off between the two parameters, namely the ID and the speed, without compromising drastically either way. A possible approach to the above trade off problem is to reduce both the wire resistivity and the dielectric constant of the material of the interlayer dielectric (ILD). This might be achieved by the use of materials such as copper, which have an inherently low dielectric. Another method is to use wires of fine pitch for lower levels (shorter wires, smaller impact) and a relaxed pitch for the upper levels (longer wires, R & C stronger impact) [1]

3.0 Analysis Techniques:

3.1 Domain Analysis:

The primary need for doing a domain analysis, be it frequency or time - is to account for the parasitics, since this addresses almost all stability issues in the interconnects. As is the case with most timing-level simulation problems, it is highly desirable to simulate the entire signal path (includes nonlinear devices and interconnections) efficiently and accurately. The usual method adopted for such simulation is to use passive, lumped, linear circuit models that might be suitable for both time and frequency domain analysis. However, time domain analysis is preferred for nonlinear models. The problem with these conventional approaches is that the simulation run-time increases super-linearly with the number of nodes in the circuit [15]. Hence, identifying a large number of nodes for analysis would hamper the efficiency of the whole process itself.

A suitable approach for improving the efficiency of circuit simulation for RLC interconnect as suggested by [4] is

  1. Macro modeling the general forms of independently using a minimum number of circuit nodes
  2. Using the macro models so obtained, in existing circuit simulators

By using reliable approximation techniques, the behavior of the interconnect within effective bandwidth is synthesized from the s-domain. The y-parameters are obtained by methods such as the Asymptotic Waveform Evaluation (AWE), which use reduced order modeling techniques. This is a one time, pre-characterization step for a specified interconnect [4].

3.2 Disturbance analysis based on harmonic distortion

Since the center frequencies of the band-pass filter associated with the discrete STFT can be freely chosen, discrete harmonic analysis as a more suitable for harmonic analysis of voltage disturbances. For real band pass filter output, real harmonic signals can be used for analysis. By using the absolute value of the filter output, the magnitude of the harmonics as a function of time can also be used for analysis. In case of the dyadic wavelet, the center frequencies of the band-pass filters are fixed once the number of scales is chosen, which leads to inconvenient center frequencies for harmonic analysis. The filter bandwidth in discrete STFT is constrained by the size of the window. Each band may contain several harmonic frequencies. The outputs from adjacent bands can be correlated. In wavelet related band-pass filers, the outputs of the different bands have less correlation. In the case of dyadic wavelet, the number of harmonic frequencies per band increases for higher bands. Both discrete STFT and dyadic wavelet are able to detect transient changes at sag-initiation and at voltage recovery. For discrete STFT, this requires that the window size chosen be of a relatively small length. Since various resolutions are used in dyadic wavelet filters, transient locations can be easily detected.

3.3 Analysis of Voltage disturbances in interconnects:

A study of voltage disturbance recordings in the time frequency-domain and in the time-scale domain establishes the suitability of the former as compared to the latter for harmonic analysis of disturbance data. The discrete Short-Time Fourier Transform (STFT) is used for the time-frequency domain; dyadic and binary-tree wavelet filters are used for the time-scale analysis.

The reason for this is that the filter center frequencies and bandwidths are inflexible, and the behavior of the harmonics is less clearly understood in the case of time-scale analysis. In the case of discrete STFT, band-pass filter outputs are well associated with the harmonics and are hence more suited to power system analysis problems. In addition to this, if the window sizes are well defined i.e. properly chosen (as the design may demand), discrete STFT is also useful for detection and analysis of transients in a voltage disturbance. Discrete SFT is used for time-frequency analysis of non-stationary signals, in cases where the use of Fourier transform alone becomes inadequate. Discrete STFT decomposes the time-varying signal into time-frequency domain components; hence it provides an insight into the time-evolution of each signal component.

3.4 Mathematical Models:

Several mathematical models have been suggested as in [5], [6], [8] and [11]. Almost all of these models revolve around partial differential equations that describe the system. It is assumed that the inductance and the capacitance matrices of the coupled micro strip lines over each subinterval are constant.

The time-tested method is to use a generalized interconnect transfer function to calculate circuit responses in the frequency domain as opposed to the time domain and then using the inverse Fourier transform to predict the time-domain signals. Existing interconnect simulation models might also be used to determine the interconnect circuit model parameters. In following the above procedure, a good practice would be to account for the skin effect (in frequency dependent conductors) as also the dielectric losses discussed earlier.

Another possible approach would be to develop a genetic algorithm to extract distributed circuit parameters of transmission lines from its computed s- parameters. A sufficient amount of system information is first collected and then used by the GA to determine the inductance or capacitance matrices as in [13].

3.5 Steady State simulation techniques

Steady state simulation is a method to obtain the worst-case instantaneous voltage drop at nodes in the top-cell power distribution. This technique requires that the initial and the boundary conditions be known. There are 2 methods to deduce these conditions.

The simpler but more laborious approach would be to make a common sense guess of the values or to go by data previously deduced. This would, in effect be an iterative approach to finding the required conditions.

Alternatively, the frequency domain approach could be used, where the periodic current waveform is transformed to the frequency domain to compute the voltages in the frequency domain. This frequency is then used in the time domain to get the steady state solutions. A Fourier analysis could be used to deduce the nodal current and voltage waveforms accurately.

4.0 Heat Mechanisms in Interconnects

4.1 Self-Heating or Joule’s Heating

Joule Heating is the amount of heat produced in a conductor due to current flow, which is directly proportional to

Q  I 2, Q  R, Q  t

Q  I 2Rt/

Q = I 2 Rt/J

Where I is the current through the interconnect in Amps

R is the Resistance of the interconnect in ohms

t is the temperature and in Kelvin

J is Joule’s Mechanical equivalent of heat

4.2 Electromigration

Electromigration is the mechanism of transfer of momentum from the electrons, which move in the applied electric field, to the ions which make up the lattice of the interconnect material. Electrons conducted through a metal scatter due to the imperfections in the lattice. Thermal energy produces scattering by causing atoms to vibrate and this acts as the source of resistance of metals. The higher the temperature, the more erratic the atom is, the greater the scattering and the greater the resistivity.

Electromigration causes different kinds of failure in interconnects. They could be void failures along the length of the line (internal failures) or diffusive displacements at the terminals of the line that destroy electrical contact. Electromigration typically does not occur in semiconductors, but occurs in some semiconductor materials that are heavily doped that such that they begin to exhibit metallic conduction.

With the advent of very large-scale integrated (VLSI) circuits, thin-film metallic conductors (interconnects) are exposed to increasingly high current densities. Under these conditions, electromigration can lead to the electrical failure of interconnects in relatively short times, thereby reducing the circuit lifetime to an unacceptable level.

Figure 1. Cross-sectional view of the interconnect structure

Usually, interconnects of very small dimensions can sustain current densities up to 1012A.cm-2 since they are deposited onto large efficient single crystal silicon heat sinks.

Increased generation of voids
Current density increase
Temperature Increase
Joule heating increase

Figure 2 Thermal Chain in EM

Electromigration lifetime is determined by Javg and Self-heating is determined by Jrms. Presently, high performance interconnect design is limited by maximum values of average, RMS and peak current densities which causes it to be inconsistent. Electromigration, on the other hand, effectively decides the lifetime of the interconnects.

4.3 Mean-Time to Failure

The EM Lifetime reliability of metal interconnects is modeled by Black’s equation, which is as follows.

MTTF = A * J –n exp (Ea/ KB Tm) ------(1)

where MTTF is the Mean Time to Failure in hrs

A is a constant that depends on the geometry and microstructure of the interconnect

J is the average current density in Amps/m2

Ea is the activation energy and

Tm is the metal temperature (sum of the reference temperature and the change in temperature due to self heating).

K is the Boltzmann constant

n is a constant ranging from 1 to 7.

Thermal heating limits the maximum allowable currents and the average permissible currents in the circuit. Thermally induced open-circuit metal failure under short duration high peak currents (ESD) is also a reliability problem. Non-uniform chip temperature results because of increased scaling, device density on chip and higher clock speed, which causes higher power dissipation and more thermal effects.

5.0 Theory and Problem Formulation:

Electromigration analysis is separated into two steps. The first step checks for violations of the current density limits, and the second step assess the mean-time-to-failure (MTTF) for all wire segments. While most interconnect segments exhibit AC current behavior, almost every signal interconnect line on a chip includes interconnect segments that exhibit DC current behavior. Therefore signal wires must be checked for both average and RMS current density violations. Hence the cumulative probability of failure for a projected lifetime has to be determined. Dormant faults can drastically affect the MTTF.

Voltage variations at the nodes in the power distribution network are in response to the time varying currents drawn / injected by the different components in the circuit. This means that the logic gate delays in digital circuits are a direct indication of the supply voltage variations. To develop an electrical model for the same would be a better way to go about the process of error detection and for further reliability tests.

In any well-defined power distribution network, the high-frequency components of the current-demand or the cycle-cycle changes in the current demand are predominantly met by the on-chip decoupling capacitance. Hence the decoupling capacitance would be indicative of the extent of variation of the primary parameters. Also, a measure of the Mean Time to Failure will give us a good estimate of the circuits’ lifetime and a measure of its robustness. While analyzing electromigration effects in aluminum interconnects, accurate estimates of the current distributions and the temperature have to be made. The EM tools used for this purpose are Sonnet and Silvaco. These tools are inherently limited in their approach since they account for just the 2-d effects of heat flow. Hence the MTTF values generated are at best indicative of the range of the MTTF.


Layout
Simulation
Current Density Calculation
Schematics
Module generation
Current Density Visualization
Current Density Verification

Figure 3: Current Density Verification flow

5.1 Current Density Profiling and Determination

The current density estimate of a microstrip interdigital bandpass filter with a center frequency of 4.75 GHZ and a bandwidth of 340 MHZ was done. The filter consists of two impedance-transforming sections on the left and right sides and 3 resonator elements in between. This circuit was obtained from the Sonnet tutorial and modified for simple simulation purposes. Each resonator element is a quarter-wavelength long at the midband frequency and is short-circuited at one end and open-circuited at the other end. The short-circuiting of the resonator elements is achieved in this example by attaching the ends of the elements to the top and bottom box walls. All box walls in Sonnet are perfect grounds [10]

The EM simulation yielded the current density profile out and a characteristic plot . The idea is to use this data to find out the hotspots in the circuit and then import this data in the script file, which will also have inputs from the Cadence netlist of the design and eventually compute the MTTF value.

5.2 Current Density Exponent, n:

For a 1.8 um wide x 0.85 um thick x 250 um long straight structure with activation energy, Ea of 0.95eV [7]. Sakimoto et al. [5], it was reported that if the metal temperature can be accurately estimated, the value of n should be 2, which is same as that proposed in Black’s model. Thus we have n=2 as the default value [4].

As a variation to the MTTF model above, an alternate model that includes a critical current density expression is also used in the industry. The equation reads as follows