Avoiding Circuit Board Disasters
Simple Rules for Avoiding Circuit Board Disasters
After a week, you've gotten your PCB's back from the vendor. They are loaded and ready to go.
You power up the board and....nothing. You begin tracing the signals through the board using the standard debugging techniques. Soon, you realize that none of the signals are going where they are supposed to. You pull the schematics and start trying to assess the damage, as your boss is standing over you wondering when the prototype will be ready to use by the software group. Soon, you discover that so many traces are misrouted that the board can't be repaired.
If you've had this experience, you aren't alone. Most engineers have gotten a board back like this.
Following a few simple rules in your board design will help keep you out of how water:
RULE #1: If you can't make it perfect, make it repairable.
Trace cuts, haywires, and lifting component leads are a few of the things you can do to fix mistakes on a circuit board. Often, the board will have to be sent through the design process again for some other reason, where all these reworks can be eliminated from the final product with no additional cost.
If you can't fix the problems, then the only option is to hurriedly fix the layout (which sometimes creates more problems) and pay for a fast turn from the PCB vendor. The project delay and fast turn costs will draw more attention to your mistakes than a few haywires.
RULE #2: Avoid tying unused inputs (and outputs) directly to ground on through-hole boards.
Unused inputs should be tied to a stable voltage source to avoid oscillations and (for CMOS) excessive power consumption from indeterminate levels at the inputs.
But if you tie an input to ground on a through-hole board, you will create a structure that looks like this:
If you decide that you need those inputs later, you will be hard pressed to separate them from the ground plane.
Consider adding a resistor, or providing instructions to the layout technician to run a trace a short distance from the through-hole out, away from the component. This trace can be cut if you need the inputs for future use.
A co-worker once ties all the inputs and outputs to ground on a circuit board. Outputs, should of course, never be tied to ground.
RULE #3: Avoid Ball Grid Arrays
BGA's are great for high-frequency, high-density interconnects but they are almost impossible to troubleshoot and repair on a new prototype board.
You can probe a through-hole PGA from the solder side; you can probe an SMT from the component side. But BGA's can't be probed from anywhere, unless you have made special arrangements for test vias with your PC Layout Technician.
If you must use a BGA part, consider using an adapter (such as ------) to transform it to a through-hole device. You will lose some high-frequency performance on your prototype, but that can be restored in a future revision once you have fixed static logic problems.
RULE #4: Double check all parts geometries, especially those for unusual parts
Engineers often assume that the schematic uniquely identifies a final circuit board. In fact, there are many other pieces of information which are built into your CAD system which will determine how your board comes out.
The most significant piece of layout information is called the part "geometry" - it is a drawing that maps the pin numbers of your schematic to a physical shape and pad layout.
For integrated circuits, there will usually be at least two geometries - one for SMT, one for through-hole. It's usually obvious from the early drawings if you chose the wrong 74LS244, or if the layout technician put in the wrong pad layout.
For connectors, there can be lots of geometries depending on how the manufacturer or design librarian thought the part would be used. Two connectors can have identical pad layouts, but different pin numbering schemes. The most common mixups occur when the engineer uses one numbering scheme for a connector, and then specifies a component with a different numbering system.
In some cases, two connectors can be physically identical from the PCB point of view - the only difference is the numbering system. Connectors that go to ribbon cables often uses a numbering system which differs from that of a connector which interfaces to discrete wires:
Figure 3 - How to really scramble a layout
(10-pin connector)
Be especially wary of edge connectors - it's possible to "flip" an edge connector. You won't be able to tell the difference on a layout, but you will once you try to plug it in.
RULE #5: Take your time to verify the layout before submitting it
This is the most difficult one. When a project is behind schedule, and your company is paying an extra $500 for a 5-day turn, it's not easy to ask for an extra day.
But it's precisely at the times when things are crunched when you want to spend the time double checking your design. The same engineers who rush a design out the door don't seem to mind spending several days finding and repairing all the mistakes.
Plan to spend a day after the layout is completed checkout out your designs. Getting the time worked into the schedule will make it easier for all concerned.
RULE #6: Check the netlist
Schematic layout tools are great for communicating design information, but their graphical nature makes them imprecise. Some tools allow you to place a piece of text over a pin number, effectively hiding the actual number. Other tools may allow you to place two pins on top of each other. Or maybe the tool allows you to run a piece of wire "behind" a part where it is invisible. And sometimes, the tool may just lose its mind and scramble all your connections.
A good read of the netlist will identify most of these problems.
For a defense against these and other problems, see problem #5.
At a minimum, you should ask for the following from your layout tech:
Almost all layout packages will let you generate a text based netlist. Print out the portions for the IC's and for the connectors. Port the netlist with DOS or Excel if you have to.
Compare these portions of the netlists against the manufacturer's pinouts. This is a very easy to check your design.
TIME REQUIRED: About 1 hour once you've done it before
EXAMPLE:
grep U10 netlist >vdd.txt
Rule #7: Triple-Check all Ground and Power Connections: These connections are among the most difficult to troubleshoot and repair.
Most modern high-frequency IC's have multiple power and ground connections. Your design may work even through you have only connected 1 of 4 possible power pins. If you measure the voltage on the other power pins, it will still read Vdd, because all the power pins are connected internally.
On the first pass, make sure all the power and ground pins are going SOMEWHERE. The most common mistake is to not hook them up.
On the second pass, make sure they are going to the right place. Your design has multiple power supplies (5V and 3.3V). Some integrated circuits have "dirty" and "clean" supply connections - make sure you've connected these properly.
EXAMPLE:
grep Vdd netlist >Vdd.txt
grep Gnd netlist >vnd.txt
Rule #8: Get a trace map showing all the signal layers, color coded. Pick a few critical components and trace the wires to make sure they are going where
you expect them. Realistically, you can't do this to every trace. But if you can pick 1 or 2 components, and trace 3 or 4 wires, you will at least be able to identify cases where something has really scrambled your design.
Rule #9: For space constrained boards, get a 1-1 plot of your design, mount it to a piece of cardboard or foam core, and make sure it fits. This is especially important for designs that are supposed to fit into tight spaces in existing pieces of equipment. If you load the components on the board, you may find out that that connector sticks up higher than you expected, and will not clear a piece of equipment. Or that resistor pack may be too close to the edge of the board, so it won't slide into its rails.
Rule #10: Trace out Clock Nets to find diabolical couplings:
You can afford to let all your data and address lines stomp on each other as much as you like. That problem can always be fixed by extending the clock speed, which will presumable allow for more setting time.
But clock-line coupling is another thing. No matter what you do, this kind of coupling will always occur in the temporal region where it does the most damage. The only after-the-fact fix involves increasing the transition time, which can be accomplished by inserting a series resistor immediately after the driver (an alternate approach, addition of a capacitor near the driver to increase the line load, can also be used but it may create additional noise problems as the drivers are forced to source more current to drive the increased load).
Don't think that just because your design is running at a low clock speed, that you are off the hook. The only relevant parameters are the slew rate of the clock and data lines.
For example, if your data line couples to your clock enough to cause a false clocking, it doesn't matter if you are running at 1 MHz or 100 MHz - you are still going to get a false clock when
The reverse case - a clock line coupling to the data lines - is just as bad. The coupling noise from the clock will appear at the worst place - just where the receiver is sampling it.
Consider all the clock lines, not just the "system clock." Clock lines can be found on peripheral devices, boundary scan networks, non-volatile RAM chips.