Asynchronous and Synchronous Design Techniques for Communication Systems Applications
Miloš Krstić
Designing modern wireless communication systems is a very challenging task. The complexity of digital systems grows enormously. The increasing demands of wireless applications create several problems for system design and integration. The following issues will have the main importance in future: integration of complex systems, timing closure including clock generation and control, system noise characteristic, and power consumption for mobile applications.
Most digital systems designed today operate synchronously. However, the system blocks can internally operate synchronously and communicate asynchronously. Such systems are known as Globally Asynchronous Locally Synchronous (GALS) systems.In this presentation a novel GALS technique applicable to wireless communication systems will beintroduced. The proposed concept is intended for point-to-point communication with very intensive but bursty data transfer between the system blocks.
The GALS technique introduced here is based on a request-driven operation of locally synchronous modules. The key idea behind this request-driven approach is that a module can use the input request signal as its clock while receiving a burst of data. Inactivity of the request line is detected with a special time-out circuitry. When time-out occurs, clocking of the locally synchronous module is handed over to a local ring oscillator or an external clock source. This allows emptying of internal pipeline stages of a locally synchronous module after a burst of data was received.
Based on this concept, a practical hardware implementation of an asynchronous wrapper is proposed. The asynchronous wrapper consists of several components, with different complexity and structure. The developed wrapper is applied to the design of an IEEE 802.11a compliant baseband processor with the aim to alleviate the problems of system integration, timing closure, clock skew, power consumption and electro-magnetic interference (EMI). The baseband processor is partitioned into a set of different GALS blocks. In order to control the complex dataflow between the blocks, some additional asynchronous blocks for providing join, fork, and data-rate adaptation functions between the GALS blocks were proposed.
The complete baseband processor including GALS wrappers is integrated, synthesized, layouted, and finally fabricated. In this talk the results of the measurements will be presented and discussed. The GALS design is compared with a synchronous version of the baseband processor with implemented clock-gating as power saving technique. In our experimental setup we have measured similar dynamic power consumption, 30% reduction in instantaneous supply voltage variations, and 5 dB reduction in spectral noise.
Keywords: GALS, System Integration, Asynchronous design, EMI, BIST