Assignment VHDL
Index
a. 4-bit Full Adder
b. 4-bit Counter
c. Decoder 2 to 4 Line
d. Decoder 3 to 8 Line
e. Half Adder
f. Half Subtractor
g. Encoder
h. Flip-Flop
i. Multiplexer
j. DeMultiplexer
k. Parity Checker
l. JK Flip-Flop
m. BCD Counter
n. Any Sequence
o. Simulation:- Test bench waveform; test bench
1. 4-bit Full Adder
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity FA _4bit is
PORT (Signal a,b : in std_logic_vector(3 downto 0);
Signal cin : in std_logic;
Signal sum : out std_logic_vector(3 downto 0);
Signal cout : out std_logic
);
End FA_4bit;
Architecture behave of FA_4bit is
Signal c : std_logic_vector (4 downto 0);
Begin
Process (a,b,cin,c)
Begin
C(0) < cin;
for I in a’range loop
Sum(i) <= a(i) xor b(i) xor c(i);
C(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i));
End loop;
Cout <= c(c’HIGH);
.UCF file for FPGA XC3S400
NET “a<0>” LOC = “p33”
NET “a<1>” LOC = “p26”;
NET “a<2>” LOC = “p24”;
NET “a<3>” LOC = “p22”;
NET “b<0>” LOC = “p37”;
NET “b<1>” LOC = “p36”;
NET “b<2>” LOC = “p35”;
NET “b<3>” LOC = “p34”;
NET “cin” LOC = “p42”;
NET “cout” LOC = “p133”;
NET “sum<0>” LOC = “p143”;
NET “sum<1>” LOC = “p140”;
NET “sum<2>” LOC = “p139”;
NET “sum<3>” LOC = “p138”;
Truth table for Full Adder
cin / input / outputSw1 a3 / Sw2 a2 / Sw3 a1 / Sw4 a0 / Sw5 b3 / Sw6 b2 / Sw7 b1 / Sw8 b0 / LE5 Cout / LED4 Sum3 / LED3 Sum3 / LED2 Sum1 / LED1 Sum0
0 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 0
0 / 0 / 0 / 0 / 0 / 0 / 0 / 0 / 0 / 0 / 0 / 0 / 0 / 0
0 / 0 / 0 / 0 / 1 / 0 / 0 / 1 / 0 / 0 / 0 / 0 / 1 / 1
0 / 1 / 0 / 0 / 0 / 1 / 0 / 0 / 0 / 1 / 0 / 0 / 0 / 0
0 / 1 / 1 / 1 / 0 / 1 / 0 / 1 / 1 / 1 / 1 / 0 / 0 / 1
0 / 1 / 1 / 0 / 1 / 1 / 0 / 0 / 1 / 1 / 0 / 1 / 1 / 0
;
2. 4-bit Counter
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity Counter_4bit is
PORT ( clk, reset : in std_logic;
Cnt_en : in std_logic;
Dout : out std_logic_vector ( 3 downto 0)
);
End Counter_4bit;
Architecture behave of Counter_4bit is
Signal cnt_state : std_logic_vector (7 downto 0);
Begin
Process (clk, reset, cnt_en)
Begin
If(reset = ‘1’) then
--asynchronous reset
Cnt_state <= “00000000”;
Elsif (clk’event and clk=’1’ ) then
If (cnt_en = ‘1’) then
Cnt_state <= cnt_state+1;
End if;
End if;
End process;
Dout <= cnt_state (6 downto 3);
End behave;
.UCF file for FPGA XC3S400
NET “clk” LOC = “p180”;
NET “cnt_en” LOC = “p22”;
NET “dout<0>” LOC = “p143”;
NET “dout<1>” LOC = “p140”;
NET “dout<2>” LOC = “p139”;
NET “dout<3>” LOC = “p138”;
NET “reset” LOC = “p204”;
3. Decoder 2 to 4 Line
Library IEEE;
Use ieee.std_logic_1164.all;
Entity decode2to4 is
PORT ( a,b, enable : in std_logic;
z : out std_logic_vector ( 3 downto 0)
);
End decode2to4;
Architecture DECODE_Concurrent of decode2to4 is
Begin
Z(0) <= ‘1’ when ((enable =’1’) and (a=’0’) and (b=’0’)) else ‘0’;
Z(1) <= ‘1’ when ((enable =’1’) and (a=’0’) and (b=’1’)) else ‘0’;
Z(0) <= ‘1’ when ((enable =’1’) and (a=’1’) and (b=’0’)) else ‘0’;
Z(0) <= ‘1’ when ((enable =’1’) and (a=’1’) and (b=’1’)) else ‘0’;
End DECODE_Concurrent;
.UCF file for FPGA XC3S400
NET “a” LOC = “p22”;
NET “b” LOC = “p24”;
NET “a” LOC = “p22”;
NET “enable” LOC = “p26”;
NET “z<0>” LOC = “p143”;
NET “z<1>” LOC = “p140”;
NET “z<2>” LOC = “p139”;
NET “z<3>” LOC = “p138”;
Truth Table for 2 to 4 decoder
Sw S3 input En / Sw S2 input a / Sw S2 input a / LED4 o/p Y3 / LED3 o/p Y2 / LED2 o/p Y1 / LED1 o/p Y01 / 0 / 0 / 0 / 0 / 0 / 1
1 / 0 / 1 / 0 / 0 / 1 / 0
1 / 1 / 0 / 0 / 1 / 0 / 0
1 / 1 / 1 / 1 / 0 / 0 / 0
4. Decoder 3 to 8 Line
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity decoder3to8 is
PORT ( signal sel : in std_logic_vector( 2 downto 0);
Signal en : in std_logic;
Signal Y : out std_logic_vector( 7 downto 0)
);
End decoder3to8;
Architecture behave of decoder3to8 is
Begin
Process ( sel, en)
Begin
Y <= “11111111”;
If(en=’1’) then
Case sel is
When “000” => Y(0) <= ‘0’;
When “000” => Y(0) <= ‘0’;
When “001” => Y(1) <= ‘0’;
When “010” => Y(2) <= ‘0’;
When “011” => Y(3) <= ‘0’;
When “100” => Y(4) <= ‘0’;
When “101” => Y(5) <= ‘0’;
When “110” => Y(6) <= ‘0’;
When “111” => Y(7) <= ‘0’;
End case;
End if;
End process;
End behave;
.UCF file for FPGA XC3S400
NET “en” LOC = “p33”;
NET “sel<0>” LOC = “p26”;
NET “sel<1>” LOC = “p24”
NET “sel<2> LOC = “p22”;
NET “Y<0>” LOC = “p143”;
NET “Y<1>” LOC = “p140”;
NET “Y<2>” LOC = “p139”;
NET “Y<3>” LOC = “p138”;
NET “Y<4>” LOC = “p133”;
NET “Y<5>” LOC = “p132”;
NET “Y<6>” LOC = “p131”;
NET “Y<7>” LOC = “p130”;
5. Half Adder
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity HA is
PORT (X, Y : in std_logic;
SUM, Carry : out std_logic
);
End HA;
Architecture behave of HA is
begin
Sum <= X xor Y;
Carry <= X and Y;
End behave;
.UCF file for FPGA XC3S400
NET “X” LOC = “p22”;
NET “Y” LOC = “p24”;
NET “SUM” LOC = “p140”;
NET “Carry” LOC = “p143”;
6. Half Subtractor
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity HS is
PORT (X, Y : in std_logic;
Diff, Borrow : out std_logic
);
End HS;
Architecture behave of HS is
begin
Diff <= X xor Y;
Borrow <= NOT X and Y;
End behave;
.UCF file for FPGA XC3S400
NET “X” LOC = “p22”;
NET “Y” LOC = “p24”;
NET “Diff” LOC = “p140”;
NET “Borrow” LOC = “p143”;
7. Encoder
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity encoder is
PORT (
Reset : in std_logic;
Clk : in std_logic;
D_in : in std_logic_vector (7 downto 0);
D_out : out std_logic_vector (2 downto 0)
);
End encoder
Architecture behave of encoder is
Begin
Process(reset, clk, D_in)
Begin
If (reset=’1’) then
D_out <= “000”;
Elsif (Clk’event and Clk = ‘1’) then
Case D_in is
When “00000001” => D_out <= “000”;
When “00000010” => D_out <= “001”;
When “00000100” => D_out <= “010”;
When “00001000” => D_out <= “011”;
When “00010000” => D_out <= “100”;
When “00100000” => D_out <= “101”;
When “01000000” => D_out <= “110”;
When “10000000” => D_out <= “111”;
End case;
End if;
End process;
End behave;
.UCF file for FPGA XC3S400
NET “clk” LOC = “p180”;
NET “D_in<0>” LOC = “p22”;
NET “D_in<1>” LOC = “p24”;
NET “D_in<2>” LOC = “p26”;
NET “D_in<3>” LOC = “p33”;
NET “D_in<4>” LOC = “p34”;
NET “D_in<5>” LOC = “p35”;
NET “D_in<6>” LOC = “p36”;
NET “D_in<7>” LOC = “p37”;
NET “D_out<0>” LOC = “p143”;
NET “D_out<1>” LOC = “p140”;
NET “D_out<2>” LOC = “p139”;
8. Flip-Flop
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity D_flipflop is
PORT (
Clk : in std_logic;
Din : in std_logic;
Dout : out std_logic
);
End D_flipflop;
Architecture behave of D_flipflop is
Begin
Process ( clk, Din)
Begin
If clk’event and clk=’1’ then -- using rising edge of the clock
Dout <= Din;
End if;
End process;
End behave;
.UCF file for FPGA XC3S400
NET “clk” LOC = “p180”;
NET “Din” LOC = “p22”;
NET “Dout” LOC = “p143”;
9. Multiplexer
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity Mux is
PORT (
Sel : in std_logic_vector (1 downto 0);
A,B,C,D : in std_logic;
Y : out std_logic
);
End Mux;
Architecture behave of Mux is
Begin
Process ( A,B,C,D, Sel)
Begin
Case sel is
When “00” => Y <= A;
When “01” => Y <= B;
When “10” => Y <= C;
When “11” => Y <= D;
End case;
End process;
End behave;
.UCF file for FPGA XC3S400
NET “Sel<0>” LOC = “p34”;
NET “Sel<1>” LOC = “p35”;
NET “A” LOC = “p22”;
NET “B” LOC = “p24”;
NET “C” LOC = “p26”;
NET “D” LOC = “p33”;
NET “Dout” LOC = “p143”;
10. DeMultiplexure
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity DeMux is
PORT (
A : in std_logic;
SEL : in std_logic_vector(1 downto 0);
Dout : out std_logic_vector(3 downto 0);
);
Architecture behave of DeMux is
Begin
Process(SEL,A)
Begin
Case SEL is
when “00” => Dout <= (0 => A, other <= ‘1’);
when “01” => Dout <= (1 => A, other <= ‘1’);
when “00” => Dout <= (2 => A, other <= ‘1’);
when “00” => Dout <= (3 => A, other <= ‘1’);
when others => Dout <= NULL;
end case;
end process;
end behave;
.UCF File
NET “A” LOC = “P22”;
NET “SEL<0>” LOC = “P24”;
NET “SEL<1>” LOC = “P26”;
NET”Dout<0>” LOC = “P143”;
NET “Dout<1>” LOC = “140”;
NET “Dout<2>” LOC = “P139”;
NET “Dout<3>” LOC = “P138”;
11. Parity Checker
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity Parity_Checker is
PORT (
A,B,C : in std_logic;
Y : out std_logic
);
End Parity_Checker;
Architecture behave of Parity_Checker is
signal X : std_logic;
Begin
X <= A xor B;
Y <= X xor C;
End behave;
.UCF file for FPGA XC3S400
NET “A” LOC = “p22”;
NET “B” LOC = “p24”;
NET “C” LOC = “p26”;
NET “Y” LOC = “p143”;
12. JK Flip-Flop
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity JKFF is
PORT (
J,K : in std_logic;
Q, QBar : out std_logic
);
End;
Architecture behave of JKFF is
Signal Qin : std_logic;
Begin
Q <= Qin;
QBar <= NOT Qin;
Process (clk)
Begin
If (clk’event and clk = ‘0’) then
If (J=’1’) then
Q < = ‘1’;
End if;
If (K=’1’) then
QBar <= ‘1’;
End if;
If (J=’1’ and K=’1’ ) then
Qin <= NOT Qin;
End if;
End if;
End process;
End;
.UCF File
NET “clk” LOC = “p180”;
NET “J” LOC = “p22”;
NET “K” LOC = “p24”;
NET “Q” LOC = “p143”;
NET “QBar” LOC = “p140”;
13 BCD Counter
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity BCDCounter is
PORT (
Clk,reset, count, count_En : in std_logic;
Dout : out std_logic_Vector (3 downto 0);
Count_State : inout std_logic(7 downto 0);
);
Behaviour Simulation
There are two options to simulate the ISE design.
1. Specifying stimulus inputs graphically called test bench waveform (not available in version 10 and above)
2. Specifying input stimulus using VHDL test bench (Available in all higher versions)
This tutorial explains the behavior simulation using VHDL test bench techniques for the 4-bit counter created in assignment-2 above. The steps are:
1. Create a project (4-bit counter) and enter the code given at index (b).
2. In the project menu, click new source.
3. Create a pro
Procedure for Schematic Draw (Structureal Modeling using Schematc Drawing
ISE/WebPACK Simulation:
This section introduces the ISim simulator included with ISE. At this point you should have a project like that in section 5 which contains the description of a combinational logic circuit. Consideration is given later to state machines.
Simulation involves a special file called a test bench or test fixture. Following version 10.1 32-bit, ISE no longer includes a graphical tool to generate test benches. Rather, an ISE tool generates a skeleton of a test bench so that a minimum of typing is required.
Here we consider such a simple VHDL test bench. Xilinx provides application notes[?] that may be helpful.
Make a Testbench File After a skeleton testbench is created you will modify its contents. Be sure that all your work is saved or you may end up with a fairly empty skeleton testbench le. If you are making a testbench for a flip-flop, state machine, or other registered logic then make the skeleton testbench file using the following but making appropriate substitutions. The testbench file name will be different as will the entity name and the signals. At the point where you assign the stimulus input go to section 7
a. Open new source
b. In the New Source Wizard pop-up window enter the following. The term Default refers to a given value which should not be changed. Click Next
c. The next window asks you to select a source le. Click to select 'fadd' then click Next
d. The next window is a summary of your choices and values. Review the list then click 'Finish'.
e. If the test bench le doesn't automatically open then open the le. Under the Options pane or process pane look for and click on the Design tab. You might have to click the left arrow just to the right to bring the Design tab into view.
• Look in the Hierarchy pane, click to select the 'Simulation' button, check that the 'Behavioral' choice is made and double click on 'fadd_fadd_sch_tb' so the corresponding test bench le appears in the text editor window.
A test bench is analogous to a laboratory test bench, which has signal generators, and test gear. We will use the test bench to describe the inputs and rather than using the test gear to verify the results, we will visually examine the simulator output waveform.